Power Grid Analysis in VLSI Designs - SERC

dydx=y⊕yx = 1 x = 0(1)It was shown in [5] that, if the inputs x I to boolean logic are (spatially) independent, then thedensity of its output y is given by:ndyD( y)= ∑ P() D(xi)(2)dxii=1In (2), it is assumed that all inputs are independent. This can lead to inaccuracy where primaryinputs will be diverging and than reconverging to primary outputs – they are not really spatiallyindependent. However, at a block, the primary inputs can be considered pretty muchindependent and hence the above approach can be modeled more accurately if the wholeblock’s boolean difference is computed.Given the signal probability and toggle density values at the primary inputs of a logic circuit, asingle pass over the circuit, using (2), gives the density at every node. Note that apart fromestimating toggle densities at the output node, we also need to calculate output signalprobabilities to do toggle density estimation of subsequent circuit logic. This is simple for twoinput AND gate.P(Y) = P(A)*P(B)orP(Y) = 1 – P(A)P(B) for NAND gate.2.3 Multi-million gate solutionWhen we apply the above approach, it gives good results for designs which are small and canbe analyzed flat and dominated by combinational logic. Beside, it is always not possible to runflat due to other logistic concerns like blocks are designed first or rest of the design is being30