Power Grid Analysis in VLSI Designs - SERC
Power Grid Analysis in VLSI Designs - SERC
Power Grid Analysis in VLSI Designs - SERC
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For large T, D(x) becomes time <strong>in</strong>variant function and hence there is no need to accountfor temporal correlation.Toggle Frequency: If a node x is toggl<strong>in</strong>g n(T) times over a time <strong>in</strong>terval of lengthT, then the toggle frequency F(x) is def<strong>in</strong>ed as:F(x) = n(T)/(2*T) where T is very huge time (<strong>in</strong>f<strong>in</strong>ite ideally)Example, if the node is switch<strong>in</strong>g at 20 MHz, it is expected that the node will switch 2times <strong>in</strong> 50 ns. As it can be seen, the toggle frequency can be converted to transitiondensity or switch<strong>in</strong>g activity by the follow<strong>in</strong>g equation,Toggle density = #of transitions/Period = Switch<strong>in</strong>g ActivityAll the three terms mentioned above are used <strong>in</strong>terchangeably <strong>in</strong> this document.It should be noted that toggle frequency of a node has no direct relation with the clockdoma<strong>in</strong>(s) <strong>in</strong> which node (or logic) exists. We have used the clock doma<strong>in</strong> frequency toupper bound the toggle frequency calculated by our approach.Signal Probability: Signal probability P(x) at a node x is def<strong>in</strong>ed as the averagefraction of clock period <strong>in</strong> which the stead state value of x is logichigh.2.2 Toggle Activity EstimationThis section gives overview of Farid Najm’s work.Boolean difference of output is computed with respect to each <strong>in</strong>put p<strong>in</strong>. Boolean difference offunction y (output) depends on x(each of the <strong>in</strong>put). It is def<strong>in</strong>ed as:29