Power Grid Analysis in VLSI Designs - SERC

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STATICDYNAMICapproach.Vector-less approach.Many times gives upper bound.Modeling of certain element (hardmacro/complex block) is difficult.Very fast. (few minutes-hours)Lot of research into products for averagepower estimation.Synopsys has: Power CompilerVector based approach. Hence quality is as good asinput vectors. Imagine number of patterns possiblefor 100 inputs block.Gives accurate result.Since it is vector based, functional models can beused during simulation.Very slow.(few days-weeks)Can give instantaneous power.Synopsys has: Power Mill (Nano Sim)Table 2.1 Comparison of Static vs Dynamic approaches for Power EstimationThis work describes the approach used for toggle frequency estimation and its limitations.Further it proposes solution to handle these limitations which makes the approach usable forbig designs.Few terms are used below to clarify discussion:Transition Density: If a logic signal x(t) makes n(T) transitions in a time internal oflength T, then the transition density of x(t) is defined as:D(x) = n(T)/T where T is very huge time (infinite ideally)28
For large T, D(x) becomes time invariant function and hence there is no need to accountfor temporal correlation.Toggle Frequency: If a node x is toggling n(T) times over a time interval of lengthT, then the toggle frequency F(x) is defined as:F(x) = n(T)/(2*T) where T is very huge time (infinite ideally)Example, if the node is switching at 20 MHz, it is expected that the node will switch 2times in 50 ns. As it can be seen, the toggle frequency can be converted to transitiondensity or switching activity by the following equation,Toggle density = #of transitions/Period = Switching ActivityAll the three terms mentioned above are used interchangeably in this document.It should be noted that toggle frequency of a node has no direct relation with the clockdomain(s) in which node (or logic) exists. We have used the clock domain frequency toupper bound the toggle frequency calculated by our approach.Signal Probability: Signal probability P(x) at a node x is defined as the averagefraction of clock period in which the stead state value of x is logichigh.2.2 Toggle Activity EstimationThis section gives overview of Farid Najm’s work.Boolean difference of output is computed with respect to each input pin. Boolean difference offunction y (output) depends on x(each of the input). It is defined as:29
Page 1: Power Grid Analysis in VLSI Designs
Page 6 and 7: 4.4.1 Timing Information Generation
Page 8 and 9: Figure 3 1GHz, Peak: 838.2 uW......
Page 11 and 12: AbstractPower has become an importa
Page 13 and 14: 1 Introduction1.1 MotivationVLSI in
Page 15 and 16: Further, Figure 1.3 shows that ther
Page 17 and 18: proposed in a few papers. In this t
Page 19 and 20: • Degradation in switching speeds
Page 21 and 22: Second, today’s design has huge P
Page 23 and 24: Figure 1.6 Total power break up int
Page 25 and 26: CMOSDieAcronym for Complimentary Me
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Page 31 and 32: done hierarchically or there is reu
Page 33 and 34: A Sample SDC file with above comman
Page 35 and 36: Some of the care needs to be taken
Page 37 and 38: Figure 2.5 Timing Arcs in extracted
Page 39 and 40: 3 Power Estimation3.1 OverviewAccur
Page 41 and 42: In this work, above power component
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Page 45 and 46: Based on power sensitivity and tool
Page 47 and 48: with SPICE. Power Mill is dynamic s
Page 49 and 50: DREPGENDREPFILE+ DATAGENFUNCTDLRAND
Page 51 and 52: 3.4.3 Interconnect setupAll the cir
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Page 55 and 56: Design TFC + Power Compiler Runtime
Page 57 and 58: Design Name CLK Power Total Power %
Page 59 and 60: DesignNamePowerCompilerProposedAppr
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Page 63 and 64: 4 Power Supply Noise Analysis4.1 Ov
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Page 69 and 70: Figure 4.6 Load vs. peak power for
Page 71 and 72: 3. The temporal correlation between
Page 73 and 74: Each such armRepresents resistance
Page 75 and 76: Characterized data was transformed
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of any node. Alternatively frequenc
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Cell Char @ fix frequency(10MHz in
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We executed the flow as explained i
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Circuit%Drop inaverage activity%Dro
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4.6 SummaryWe proposed novel PG net
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network but causing huge dynamic IR
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Power SwitchFigure 5.2 Layout of 1M
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power network start getting charged
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Note that the 1 stcharacterization
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• Maximum current surge that will
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gates in the virtual network or mor
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Vdesired (mV)Actual#SwitchesSwitche
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5.4 SummaryThere are various techni
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5. Power Up analysis for MTCMOS bas
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108
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21. F.N. Najm, R.Burch, P. Yang, an
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62. H. Mehta, R.M.Owens, M.J.Irwin,
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Appendix B Sample SPEF Format*SPEF
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Appendix C Power Waveforms Analysis
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Appendix E Waveform transformation
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