Power Grid Analysis in VLSI Designs - SERC

2 Toggle Activity Estimation2.1 OverviewIn CMOS technologies, the chip components draw power supply current only during a logictransition if we ignore the small leakage current. The current is also proportional to the supplyvoltage value seen by the cell or macro. While this is considered an attractive low-powerfeature of these technologies, it makes the power estimation and voltage drop highly dependenton the switching activity inside these circuits [11][97]. It means, a more active circuit willconsume more current and hence will contribute higher Voltage drop. The activity of circuit isknown by running simulation patterns and analyzing the data. The pattern-dependence problemis serious. Often, the power of a functional block needs to be estimated when the rest of thechip has not yet been designed, or even completely specified. In such a case, very little may beknown about the inputs to this functional block, and complete and specific information aboutits inputs would be impossible to obtain.This drives pattern independent toggle activity estimation problem, often referred as vector lessapproach. Since vector less approach does not require patterns, it is also called ‘static’ whereasvector based approach is called ‘dynamic’. Table 2.1 compares these 2 approaches.STATICDYNAMICUses probabilistic approach as describedin [12] or zero delay simulation basedUses Logic simulation to generate switchingactivity or SPICE simulation to calculate power.27