Power Grid Analysis in VLSI Designs - SERC
Power Grid Analysis in VLSI Designs - SERC Power Grid Analysis in VLSI Designs - SERC
power estimation as well as addresses the challenges of toggle estimation which has variedapplications like peak power estimation, power supply noise analysis and reliability analysis.Second, Dynamic Power supply Noise estimation. In this regard, a prototype flow is developedin conjunction with Prime Time STA flow and Spice to measure Power Supply noise. The workdescribes gate characterization methodology that involves one time SPICE simulation and howthe PG network is modeled using the characterized data.Third problem addressed is power grid analysis where MTCMOS gates are inserted. The workfocuses on MTCMOS analysis challenges and key factors to focus on when a bunch of logicturns ON from OFF state. In this regard, a flow is developed to estimate peak currents oroptimize MTCMOS resistance and switches.We restrict out scope to CMOS circuits mapped on a predefined cell library and we follow thetwo step paradigm – library modeling and analysis of design using modeled information.Library modeling involves description of cells, their functional, structural or electrical behavioras needed for block or design analysis, which happens once for all. Electrical behaviormodeling happens through characterization using circuit simulator (e.g. SPICE [3]).The document is organized as below. Toggle estimation problem is addressed in chapter 2.Chapter 3 describes the various Power Estimation techniques and tools available in industryand compares the power numbers with the above toggle estimation method. Chapter 4 describesPower Supply Noise Estimation and Chapter 5 describes MTCMOS Power Up analysis. Finally,huge lists of publications are shown at the end for further reference.26
2 Toggle Activity Estimation2.1 OverviewIn CMOS technologies, the chip components draw power supply current only during a logictransition if we ignore the small leakage current. The current is also proportional to the supplyvoltage value seen by the cell or macro. While this is considered an attractive low-powerfeature of these technologies, it makes the power estimation and voltage drop highly dependenton the switching activity inside these circuits [11][97]. It means, a more active circuit willconsume more current and hence will contribute higher Voltage drop. The activity of circuit isknown by running simulation patterns and analyzing the data. The pattern-dependence problemis serious. Often, the power of a functional block needs to be estimated when the rest of thechip has not yet been designed, or even completely specified. In such a case, very little may beknown about the inputs to this functional block, and complete and specific information aboutits inputs would be impossible to obtain.This drives pattern independent toggle activity estimation problem, often referred as vector lessapproach. Since vector less approach does not require patterns, it is also called ‘static’ whereasvector based approach is called ‘dynamic’. Table 2.1 compares these 2 approaches.STATICDYNAMICUses probabilistic approach as describedin [12] or zero delay simulation basedUses Logic simulation to generate switchingactivity or SPICE simulation to calculate power.27
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- Page 13 and 14: 1 Introduction1.1 MotivationVLSI in
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- Page 57 and 58: Design Name CLK Power Total Power %
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power estimation as well as addresses the challenges of toggle estimation which has variedapplications like peak power estimation, power supply noise analysis and reliability analysis.Second, Dynamic <strong>Power</strong> supply Noise estimation. In this regard, a prototype flow is developed<strong>in</strong> conjunction with Prime Time STA flow and Spice to measure <strong>Power</strong> Supply noise. The workdescribes gate characterization methodology that <strong>in</strong>volves one time SPICE simulation and howthe PG network is modeled us<strong>in</strong>g the characterized data.Third problem addressed is power grid analysis where MTCMOS gates are <strong>in</strong>serted. The workfocuses on MTCMOS analysis challenges and key factors to focus on when a bunch of logicturns ON from OFF state. In this regard, a flow is developed to estimate peak currents oroptimize MTCMOS resistance and switches.We restrict out scope to CMOS circuits mapped on a predef<strong>in</strong>ed cell library and we follow thetwo step paradigm – library model<strong>in</strong>g and analysis of design us<strong>in</strong>g modeled <strong>in</strong>formation.Library model<strong>in</strong>g <strong>in</strong>volves description of cells, their functional, structural or electrical behavioras needed for block or design analysis, which happens once for all. Electrical behaviormodel<strong>in</strong>g happens through characterization us<strong>in</strong>g circuit simulator (e.g. SPICE [3]).The document is organized as below. Toggle estimation problem is addressed <strong>in</strong> chapter 2.Chapter 3 describes the various <strong>Power</strong> Estimation techniques and tools available <strong>in</strong> <strong>in</strong>dustryand compares the power numbers with the above toggle estimation method. Chapter 4 describes<strong>Power</strong> Supply Noise Estimation and Chapter 5 describes MTCMOS <strong>Power</strong> Up analysis. F<strong>in</strong>ally,huge lists of publications are shown at the end for further reference.26
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