Power Grid Analysis in VLSI Designs - SERC
Power Grid Analysis in VLSI Designs - SERC Power Grid Analysis in VLSI Designs - SERC
transistors and controlling signals and are used to dynamically switch off or on the powersupply to specific region in the chip. This work studies the challenges associated with usingpower switches and proposes fast analysis technique to estimate peak currents while Powerramp up of logic happens.1.2 TermsGeneric terms used in this report are described below.ASICBlockNetlistPhysical DesignRTLCharacterizationAcronym for Application Specific Integrated Circuits. A custom or semicustom integrated circuit, such as a cell or gate array, created for a specificapplication. The complexity of ASICs typically requires significant use ofCAD techniques.Also known as functional block or module. Any block within the designhierarchy instantiated one or more times that will be laid out separately isreferred to as a block module. Block modules are defined divisions of a chipbased on functionality and can be worked on independently of otherfunctional blocks.A description of the circuit. The description can be a gate-level or Register-Transfer level (RTL) one. It can also be in different languages like Verilogor VHDL or SPICE.A portion of a chip or circuit corresponding to a block module that is laidout separately using a Physical Design tool. It is also referred to as aphysical block, layout region, or layout block.Acronym for Register Transfer LevelElectrical analysis performed for the purpose of determining typical deviceperformance characteristics and/or parametric limits.24
CMOSDieAcronym for Complimentary Metal Oxide Semiconductor. An MOStechnology in which both P-channel and N-channel devices are fabricatedon the same die.A single square or rectangular piece of silicon into which a specificsemiconductor circuit has been diffused.Electromigration Particle migration in aluminum or copper thin-film or polysiliconconductors at grain boundaries as a result of high current densities.Electromigration can lead to either an open circuit condition in a conductoror a short between adjacent connectors.InterconnectTiming WindowThe metallization connecting two or more active elements on the surface ofa die; also, the wires connecting the die to the package leads.Timing window specifies the interval of each circuit node at which atransition activity is anticipated. For a single clock domain, the time intervalcan lie within a clock period. There can be more than one intervals oroverlapping intervals based on complexity of path converging to the node.Table 1.2 Generic Term Definitions1.3 Thesis outline and ContributionThere are 3 distinct problems addressed in this work.First, Average Power Estimation using probabilistic toggle estimation for multi-million gatedesigns. Unless specified by the user, the approach calculates switching probabilities as well asswitching rate at different nodes in the circuit (including primary inputs). We have studiedswitching activity calculation method with lot of literature already available and enhanced oneof the techniques to meet multimillion gate design needs. This work helps in average dynamic25
- Page 1: Power Grid Analysis in VLSI Designs
- Page 6 and 7: 4.4.1 Timing Information Generation
- Page 8 and 9: Figure 3 1GHz, Peak: 838.2 uW......
- Page 11 and 12: AbstractPower has become an importa
- Page 13 and 14: 1 Introduction1.1 MotivationVLSI in
- Page 15 and 16: Further, Figure 1.3 shows that ther
- Page 17 and 18: proposed in a few papers. In this t
- Page 19 and 20: • Degradation in switching speeds
- Page 21 and 22: Second, today’s design has huge P
- Page 23: Figure 1.6 Total power break up int
- Page 27 and 28: 2 Toggle Activity Estimation2.1 Ove
- Page 29 and 30: For large T, D(x) becomes time inva
- Page 31 and 32: done hierarchically or there is reu
- Page 33 and 34: A Sample SDC file with above comman
- Page 35 and 36: Some of the care needs to be taken
- Page 37 and 38: Figure 2.5 Timing Arcs in extracted
- Page 39 and 40: 3 Power Estimation3.1 OverviewAccur
- Page 41 and 42: In this work, above power component
- Page 43 and 44: on the required accuracy, different
- Page 45 and 46: Based on power sensitivity and tool
- Page 47 and 48: with SPICE. Power Mill is dynamic s
- Page 49 and 50: DREPGENDREPFILE+ DATAGENFUNCTDLRAND
- Page 51 and 52: 3.4.3 Interconnect setupAll the cir
- Page 53 and 54: DesignNameIN OUT Flops Boolean(gate
- Page 55 and 56: Design TFC + Power Compiler Runtime
- Page 57 and 58: Design Name CLK Power Total Power %
- Page 59 and 60: DesignNamePowerCompilerProposedAppr
- Page 61 and 62: We can approximate the average powe
- Page 63 and 64: 4 Power Supply Noise Analysis4.1 Ov
- Page 65 and 66: to be absolutely in complete alignm
- Page 67 and 68: In this work, we have maintained te
- Page 69 and 70: Figure 4.6 Load vs. peak power for
- Page 71 and 72: 3. The temporal correlation between
- Page 73 and 74: Each such armRepresents resistance
transistors and controll<strong>in</strong>g signals and are used to dynamically switch off or on the powersupply to specific region <strong>in</strong> the chip. This work studies the challenges associated with us<strong>in</strong>gpower switches and proposes fast analysis technique to estimate peak currents while <strong>Power</strong>ramp up of logic happens.1.2 TermsGeneric terms used <strong>in</strong> this report are described below.ASICBlockNetlistPhysical DesignRTLCharacterizationAcronym for Application Specific Integrated Circuits. A custom or semicustom <strong>in</strong>tegrated circuit, such as a cell or gate array, created for a specificapplication. The complexity of ASICs typically requires significant use ofCAD techniques.Also known as functional block or module. Any block with<strong>in</strong> the designhierarchy <strong>in</strong>stantiated one or more times that will be laid out separately isreferred to as a block module. Block modules are def<strong>in</strong>ed divisions of a chipbased on functionality and can be worked on <strong>in</strong>dependently of otherfunctional blocks.A description of the circuit. The description can be a gate-level or Register-Transfer level (RTL) one. It can also be <strong>in</strong> different languages like Verilogor VHDL or SPICE.A portion of a chip or circuit correspond<strong>in</strong>g to a block module that is laidout separately us<strong>in</strong>g a Physical Design tool. It is also referred to as aphysical block, layout region, or layout block.Acronym for Register Transfer LevelElectrical analysis performed for the purpose of determ<strong>in</strong><strong>in</strong>g typical deviceperformance characteristics and/or parametric limits.24
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