Power Grid Analysis in VLSI Designs - SERC

Figure 1.6 Total power break up into leakage and activeLeakage power control and power network integrity have become one of the key area ofinterest for today’s power sensitive designs. In comments on Power Consumption Problem atthe 2002 International Electron Devices Meeting, Intel chairman Andrew Grove cited off-statecurrent leakage in particular as a limiting factor in future microprocessor integration. [72]Designers have been coming out innovative way to reduce leakage power using varioustechniques – reducing device power supply and frequency of operation [73], Multi-Vt transistorusage [74-79], controlling input states [74], memory leakage reduction [75], using reverse bodybias [76], and using transistor stack [77]. A detailed study on sources of leakage power andreduction techniques can be found in [82].Several techniques are available to reduce the leakage – gated power supply using powerswitches is one of the most promising techniques. Power switches consist of several PMOS23