Power Grid Analysis in VLSI Designs - SERC

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Four, design methodologies today expect analysis to meet predefined PG noise targets. Inreality, any acceptable voltage drop is fine if we meet the required timing goals. However, thisis not done due to lack of analysis data.Five, it has been found that many times the device fail on testers due to excessive simultaneousswitching in SCAN testing. This creates serious testability issues and hence not only we need toanalyze dynamic V drop for functional mode but also some other modes like test.This work addresses the dynamic PG noise problem. The problem is also described as dynamicV drop problem in some literature. Based on the above-mentioned issues, the goal is to addressthe dynamic V drop problem with efficient runtime that addresses today’s multi million gatedesigns. The goal is to also evaluate the impact of dynamic V drop on timing.1.1.3 MTCMOS AnalysisLeakage power consists of more than half of total power in today’s ultra sub micron designs.See Figure 1.6 below.22
Figure 1.6 Total power break up into leakage and activeLeakage power control and power network integrity have become one of the key area ofinterest for today’s power sensitive designs. In comments on Power Consumption Problem atthe 2002 International Electron Devices Meeting, Intel chairman Andrew Grove cited off-statecurrent leakage in particular as a limiting factor in future microprocessor integration. [72]Designers have been coming out innovative way to reduce leakage power using varioustechniques – reducing device power supply and frequency of operation [73], Multi-Vt transistorusage [74-79], controlling input states [74], memory leakage reduction [75], using reverse bodybias [76], and using transistor stack [77]. A detailed study on sources of leakage power andreduction techniques can be found in [82].Several techniques are available to reduce the leakage – gated power supply using powerswitches is one of the most promising techniques. Power switches consist of several PMOS23
Page 1: Power Grid Analysis in VLSI Designs
Page 6 and 7: 4.4.1 Timing Information Generation
Page 8 and 9: Figure 3 1GHz, Peak: 838.2 uW......
Page 11 and 12: AbstractPower has become an importa
Page 13 and 14: 1 Introduction1.1 MotivationVLSI in
Page 15 and 16: Further, Figure 1.3 shows that ther
Page 17 and 18: proposed in a few papers. In this t
Page 19 and 20: • Degradation in switching speeds
Page 21: Second, today’s design has huge P
Page 25 and 26: CMOSDieAcronym for Complimentary Me
Page 27 and 28: 2 Toggle Activity Estimation2.1 Ove
Page 29 and 30: For large T, D(x) becomes time inva
Page 31 and 32: done hierarchically or there is reu
Page 33 and 34: A Sample SDC file with above comman
Page 35 and 36: Some of the care needs to be taken
Page 37 and 38: Figure 2.5 Timing Arcs in extracted
Page 39 and 40: 3 Power Estimation3.1 OverviewAccur
Page 41 and 42: In this work, above power component
Page 43 and 44: on the required accuracy, different
Page 45 and 46: Based on power sensitivity and tool
Page 47 and 48: with SPICE. Power Mill is dynamic s
Page 49 and 50: DREPGENDREPFILE+ DATAGENFUNCTDLRAND
Page 51 and 52: 3.4.3 Interconnect setupAll the cir
Page 53 and 54: DesignNameIN OUT Flops Boolean(gate
Page 55 and 56: Design TFC + Power Compiler Runtime
Page 57 and 58: Design Name CLK Power Total Power %
Page 59 and 60: DesignNamePowerCompilerProposedAppr
Page 61 and 62: We can approximate the average powe
Page 63 and 64: 4 Power Supply Noise Analysis4.1 Ov
Page 65 and 66: to be absolutely in complete alignm
Page 67 and 68: In this work, we have maintained te
Page 69 and 70: Figure 4.6 Load vs. peak power for
Page 71 and 72: 3. The temporal correlation between
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Each such armRepresents resistance
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Characterized data was transformed
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Do timing analysis and based on inp
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of any node. Alternatively frequenc
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Cell Char @ fix frequency(10MHz in
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We executed the flow as explained i
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Circuit%Drop inaverage activity%Dro
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4.6 SummaryWe proposed novel PG net
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network but causing huge dynamic IR
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Power SwitchFigure 5.2 Layout of 1M
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power network start getting charged
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Note that the 1 stcharacterization
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• Maximum current surge that will
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gates in the virtual network or mor
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Vdesired (mV)Actual#SwitchesSwitche
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5.4 SummaryThere are various techni
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5. Power Up analysis for MTCMOS bas
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108
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21. F.N. Najm, R.Burch, P. Yang, an
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62. H. Mehta, R.M.Owens, M.J.Irwin,
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114
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Appendix B Sample SPEF Format*SPEF
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Appendix C Power Waveforms Analysis
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Appendix E Waveform transformation
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