Power Grid Analysis in VLSI Designs - SERC

and confidence levels. Experimental results show that this method typically produces maximumpower estimates within 5% of the actual value and with a 90% confidence level by onlysimulating less than 2500 input vectors. Another technique described in [31] computes peakpowers of design while maintaining the current waveform accuracy. It models logic gates bybreaking the gates into various nodes. It then models various currents in terms of these nodeswhich are evaluated quickly during logic simulation to measure power. However, this is basedon logical simulation so extremely difficult to scale.Chen and Ling [36] proposed an approach to estimate the power supply noise based on anintegrated package-level and chip-level power bus model. Chang, Gupta, and Breuer [37]proposed an analytical model to estimate the ground bounce caused by the switching in theinternal circuitry for sub-micron VLSI circuits. Jiang, Cheng, and Deng [38] proposed aGenetic Algorithm-based approach that considered the dependence of switching noise on inputpatterns under a distributed RC model of the PG network. Zhao, Roy, and Kho proposed anevent-driven simulation based approach to calculate the worst case power supply noise under adistributed RLC model [39].There are still more challenges in this area where very little work has been done.First, to analyze Power Ground (PG) noise, worst case vectors are required using which theparasitic network of chip is simulated. Not only the whole approach needs lot of data andmemory but today’s SPICE simulators are not able to handle such complexity in terms ofruntime and capacity. Many times (read as all the time) determining the worst case vectors isnot straightforward.20