Power Grid Analysis in VLSI Designs - SERC

• Degradation in switching speeds• Reduction in Noise Margin and Driving Capability of the gatesAccording to a study on Pentium®4 [26], power supply noise can reduce clock frequency by6.5% on 130 nm node and can reduce clock frequency by 8% on 90 nm node. All these arehandled through various margins in design flow as there are no efficient solutions available toaddress dynamic V drop problem in design flow.There is some work done to estimate peak power as well as decoupling capacitor in this regard.In [27], a pattern-independent, linear time algorithm is described that estimates the maximumcurrent waveforms at various contact points in the circuit. The algorithm is first demonstratedfor simple gate delay and current models. The expression for modeling the delays and currentwaveforms for a general gate is derived and the way to extend the algorithm under moregeneral models is also described. The authors improved the work in [28]. In [29] measures ofpeak power are proposed in the context of sequential circuits, and a procedure is presented toobtain lower bounds on these measures, as well as providing the actual input vectors that attainsuch bounds. Automatic generation of a functional vector loop for near-worst case powerconsumption is attained.Paper [30] presents a statistical method for estimating the peakpower dissipation in VLSI circuits. The method is based on the theory of extreme orderstatistics and its application to the probabilistic distributions of the cycle-by-cycle powerconsumption, the maximum-likelihood estimation, and the Monte-Carlo simulation. It can beused to predict the maximum power of a VLSI circuit in the set of constrained input vectorpairs as well as the complete set of all possible input vector pairs. The simulation-based natureof the method avoids the limitations of a gate-level delay model and a gate-level circuitstructure. Also, the method produces maximum power estimates to satisfy user-specified error19