Power Grid Analysis in VLSI Designs - SERC

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switching occurring in a short period of time can cause a considerable amount of noise in thepower supply network of a circuit. Power supply noise means decrease in voltage seen by cellPower Ground nodes. Schematic of Power Network gird is shown in Figure 1.4. The resistiveparasitic R in the power distribution network is accountable for the resistive noise, which is theIR voltage drop in the PG network. Apart from R, on chip decoupling capacitance also plays abig role. The switching noise in the power distribution network must be contained to a tolerablelevel to ensure the reliability/performance of a circuit.IO PadVdd Pad Vss Pad IO PadIO PadIO PadVssPadIO Pad5Vss PadIO Pad1IO PadVdd Pad Vss Pad IO PadFigure 1.4 Schematic of Power Grid in CMOS designsExcessive voltage drops manifest themselves as glitches on the PG buses and cause:• Erroneous logic signals18
• Degradation in switching speeds• Reduction in Noise Margin and Driving Capability of the gatesAccording to a study on Pentium®4 [26], power supply noise can reduce clock frequency by6.5% on 130 nm node and can reduce clock frequency by 8% on 90 nm node. All these arehandled through various margins in design flow as there are no efficient solutions available toaddress dynamic V drop problem in design flow.There is some work done to estimate peak power as well as decoupling capacitor in this regard.In [27], a pattern-independent, linear time algorithm is described that estimates the maximumcurrent waveforms at various contact points in the circuit. The algorithm is first demonstratedfor simple gate delay and current models. The expression for modeling the delays and currentwaveforms for a general gate is derived and the way to extend the algorithm under moregeneral models is also described. The authors improved the work in [28]. In [29] measures ofpeak power are proposed in the context of sequential circuits, and a procedure is presented toobtain lower bounds on these measures, as well as providing the actual input vectors that attainsuch bounds. Automatic generation of a functional vector loop for near-worst case powerconsumption is attained.Paper [30] presents a statistical method for estimating the peakpower dissipation in VLSI circuits. The method is based on the theory of extreme orderstatistics and its application to the probabilistic distributions of the cycle-by-cycle powerconsumption, the maximum-likelihood estimation, and the Monte-Carlo simulation. It can beused to predict the maximum power of a VLSI circuit in the set of constrained input vectorpairs as well as the complete set of all possible input vector pairs. The simulation-based natureof the method avoids the limitations of a gate-level delay model and a gate-level circuitstructure. Also, the method produces maximum power estimates to satisfy user-specified error19
Page 1: Power Grid Analysis in VLSI Designs
Page 6 and 7: 4.4.1 Timing Information Generation
Page 8 and 9: Figure 3 1GHz, Peak: 838.2 uW......
Page 11 and 12: AbstractPower has become an importa
Page 13 and 14: 1 Introduction1.1 MotivationVLSI in
Page 15 and 16: Further, Figure 1.3 shows that ther
Page 17: proposed in a few papers. In this t
Page 21 and 22: Second, today’s design has huge P
Page 23 and 24: Figure 1.6 Total power break up int
Page 25 and 26: CMOSDieAcronym for Complimentary Me
Page 27 and 28: 2 Toggle Activity Estimation2.1 Ove
Page 29 and 30: For large T, D(x) becomes time inva
Page 31 and 32: done hierarchically or there is reu
Page 33 and 34: A Sample SDC file with above comman
Page 35 and 36: Some of the care needs to be taken
Page 37 and 38: Figure 2.5 Timing Arcs in extracted
Page 39 and 40: 3 Power Estimation3.1 OverviewAccur
Page 41 and 42: In this work, above power component
Page 43 and 44: on the required accuracy, different
Page 45 and 46: Based on power sensitivity and tool
Page 47 and 48: with SPICE. Power Mill is dynamic s
Page 49 and 50: DREPGENDREPFILE+ DATAGENFUNCTDLRAND
Page 51 and 52: 3.4.3 Interconnect setupAll the cir
Page 53 and 54: DesignNameIN OUT Flops Boolean(gate
Page 55 and 56: Design TFC + Power Compiler Runtime
Page 57 and 58: Design Name CLK Power Total Power %
Page 59 and 60: DesignNamePowerCompilerProposedAppr
Page 61 and 62: We can approximate the average powe
Page 63 and 64: 4 Power Supply Noise Analysis4.1 Ov
Page 65 and 66: to be absolutely in complete alignm
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Figure 4.6 Load vs. peak power for
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3. The temporal correlation between
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Each such armRepresents resistance
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Characterized data was transformed
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Do timing analysis and based on inp
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of any node. Alternatively frequenc
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Cell Char @ fix frequency(10MHz in
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We executed the flow as explained i
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Circuit%Drop inaverage activity%Dro
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4.6 SummaryWe proposed novel PG net
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network but causing huge dynamic IR
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Power SwitchFigure 5.2 Layout of 1M
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power network start getting charged
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Note that the 1 stcharacterization
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• Maximum current surge that will
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gates in the virtual network or mor
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Vdesired (mV)Actual#SwitchesSwitche
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5.4 SummaryThere are various techni
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5. Power Up analysis for MTCMOS bas
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108
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21. F.N. Najm, R.Burch, P. Yang, an
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62. H. Mehta, R.M.Owens, M.J.Irwin,
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114
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Appendix B Sample SPEF Format*SPEF
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Appendix C Power Waveforms Analysis
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Appendix E Waveform transformation
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Power Grid Analysis in VLSI Designs - SERC

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