Power Grid Analysis in VLSI Designs - SERC

1.1.1 Power EstimationOne of the challenges in Power Integrity analysis is to predict accurate power dissipation – bothaverage as well as peak - of design. Power Estimation is required for package thermal analysis,power minimization, and Power Grid design.The earliest proposed techniques of estimating power dissipation were strongly patterndependentcircuit simulation based e.g. SPICE or fast SPICE simulators [3-6]. Besides beingstrongly pattern-dependent, these techniques are too slow to be used on modern very largescaleintegrated (VLSI) circuits for which high power dissipation is a major problem.In order to improve computational efficiency, other simulation-based techniques were proposedusing various kinds of timing, switch-level, and logic simulation [7-9]. In these approaches,lookup tables are obtained by electrical simulation of the basic library elements, and thecollected data are then used during gate level simulation. These techniques generally assumethat the power supply and ground voltages are fixed, and only the supply current waveform isestimated. While they are indeed more efficient than traditional circuit simulation at the cost ofsome loss in accuracy, they remain strongly pattern-dependent and they are still slow formodern multi-million gate designs where whole chip can not be simulated together.In order to overcome the shortcomings of simulation-based techniques, research has beenfocused on probabilistic and statistical techniques for toggle estimation. The use ofprobabilities to estimate power was first proposed in [11]. In this work, a zero-delay model wasmade so that the transition probabilities could be estimated using signal probabilities. Aprobabilistic power estimation approach that does compute the toggle power and does not makethe zero-delay or temporal independence assumptions, called probabilistic simulation was16