Power Grid Analysis in VLSI Designs - SERC

instantaneous IR drop. However, there is no good analysis methodology in place to analyze thisphenomenon. Ad hoc decoupling planning and on chip intrinsic decoupling capacitance helpsto contain this noise but there is no guarantee. This work also applies average togglecomputation approach to compute instantaneous IR drop analysis for designs. Instantaneous IRdrop is also known as dynamic IR drop or power supply noise. We are proposing cellcharacterization methodology for standard cells. This data is used to build power grid model ofthe design. Finally, the power network is solved to compute instantaneous IR drop.Leakage Power Minimization has forced design teams to do complex power gating – multilevel MTCMOS usage in Power Grid. This puts additonal analysis challenge for Power Grid interms of ON/OFF sequencing and noise injection due to it. This work explains the state of arthere and highlights some of the issues and trade offs using MTCMOS logic. It further suggestsa simple approach to quickly access the impact of MTCMOS gates in Power Grid in terms ofpeak currents and IR drop. Alternatively, the approach suggested also helps in MTCMOS gateoptimization. Early leakage optimization overhead can be computed using this approach.12