Power Grid Analysis in VLSI Designs - SERC

*RES0 PREZ PREZ:0 0.11 DTP10J_0:PREZ PREZ:0 0.12 DTP10J_1:PREZ PREZ:0 0.13 DTP10J_2:PREZ PREZ:0 0.1*END*D_NET CLK 0.1*CONN*I DTP10J_0:CLK I *L 0.1 *D DTP10J*I DTP10J_1:CLK I *L 0.1 *D DTP10J*I DTP10J_2:CLK I *L 0.1 *D DTP10J*P CLK I *L 0.1*CAP0 CLK 0.11 DTP10J_0:CLK 0.12 DTP10J_1:CLK 0.13 DTP10J_2:CLK 0.14 CLK:0 0.1*RES0 CLK CLK:0 0.11 DTP10J_0:CLK CLK:0 0.12 DTP10J_1:CLK CLK:0 0.13 DTP10J_2:CLK CLK:0 0.1*END*D_NET G10 0.1*END*D_NET G5 0.1*CONN*I DTP10J_0:Q O *L 0.1 *D DTP10J*I NO210_1:A I *L 0.1 *D NO210*CAP0 DTP10J_0:Q 0.11 NO210_1:A 0.12 G5:0 0.1*RES0 DTP10J_0:Q G5:0 0.11 NO210_1:A G5:0 0.1*END*D_NET G6 0.1*CONN*I DTP10J_1:Q O *L 0.1 *D DTP10J*I AN210_0:B I *L 0.1 *D AN210*CAP0 DTP10J_1:Q 0.11 AN210_0:B 0.12 G6:0 0.1*RES0 DTP10J_1:Q G6:0 0.11 AN210_0:B G6:0 0.1 *END*CONN*I DTP10J_0:D I *L 0.1 *D DTP10J*I NO210_0:Y O *L 0.1 *D NO210*CAP0 DTP10J_0:D 0.11 NO210_0:Y 0.12 G10:0 0.1*RES0 DTP10J_0:D G10:0 0.11 NO210_0:Y G10:0 0.1117