Power Grid Analysis in VLSI Designs - SERC
Power Grid Analysis in VLSI Designs - SERC Power Grid Analysis in VLSI Designs - SERC
Appendix B Sample SPEF Format*SPEF "IEEE 1481-1997"*DESIGN "s27"*DATE "Mon Dec 13 10:05:00 1999"*VENDOR "TI"*PROGRAM "vlog2spef"*VERSION "1.0"*DESIGN_FLOW "Dummy From Verilog"*DIVIDER /*DELIMITER :*BUS_DELIMITER []*T_UNIT 1 NS*C_UNIT 1 PF*R_UNIT 1 KOHM*L_UNIT 1e-3 UH*PORTSG17 O *L 0.1G3 I *S 0.1 0.1G2 I *S 0.1 0.1G1 I *S 0.1 0.1G0 I *S 0.1 0.1PREZ I *S 0.1 0.1CLK I *S 0.1 0.1*D_NET G17 0.1*CONN*I IV110_1:Y O *L 0.1 *D IV110*P G17 O *L 0.1*CAP0 G17 0.11 IV110_1:Y 0.12 G17:0 0.1*RES0 G17 G17:0 0.11 IV110_1:Y G17:0 0.1*END*D_NET G3 0.1*CONN*I OR210_1:A I *L 0.1 *D OR210*P G3 I *L 0.1*CAP0 G3 0.11 OR210_1:A 0.12 G3:0 0.1*RES0 G3 G3:0 0.11 OR210_1:A G3:0 0.1*END*D_NET G2 0.1*CONN*I NO210_3:A I *L 0.1 *D NO210*P G2 I *L 0.1*CAP0 G2 0.11 NO210_3:A 0.12 G2:0 0.1*RES0 G2 G2:0 0.11 NO210_3:A G2:0 0.1*END*D_NET G1 0.1*CONN*I NO210_2:A I *L 0.1 *D NO210*P G1 I *L 0.1*CAP0 G1 0.11 NO210_2:A 0.12 G1:0 0.1*RES0 G1 G1:0 0.11 NO210_2:A G1:0 0.1*END*D_NET G0 0.1*CONN*I IV110_0:A I *L 0.1 *D IV110*P G0 I *L 0.1*CAP0 G0 0.11 IV110_0:A 0.12 G0:0 0.1*RES0 G0 G0:0 0.11 IV110_0:A G0:0 0.1*END*D_NET PREZ 0.1*CONN*I DTP10J_0:PREZ I *L 0.1 *D DTP10J*I DTP10J_1:PREZ I *L 0.1 *D DTP10J*I DTP10J_2:PREZ I *L 0.1 *D DTP10J*P PREZ I *L 0.1*CAP0 PREZ 0.11 DTP10J_0:PREZ 0.12 DTP10J_1:PREZ 0.13 DTP10J_2:PREZ 0.14 PREZ:0 0.1116
*RES0 PREZ PREZ:0 0.11 DTP10J_0:PREZ PREZ:0 0.12 DTP10J_1:PREZ PREZ:0 0.13 DTP10J_2:PREZ PREZ:0 0.1*END*D_NET CLK 0.1*CONN*I DTP10J_0:CLK I *L 0.1 *D DTP10J*I DTP10J_1:CLK I *L 0.1 *D DTP10J*I DTP10J_2:CLK I *L 0.1 *D DTP10J*P CLK I *L 0.1*CAP0 CLK 0.11 DTP10J_0:CLK 0.12 DTP10J_1:CLK 0.13 DTP10J_2:CLK 0.14 CLK:0 0.1*RES0 CLK CLK:0 0.11 DTP10J_0:CLK CLK:0 0.12 DTP10J_1:CLK CLK:0 0.13 DTP10J_2:CLK CLK:0 0.1*END*D_NET G10 0.1*END*D_NET G5 0.1*CONN*I DTP10J_0:Q O *L 0.1 *D DTP10J*I NO210_1:A I *L 0.1 *D NO210*CAP0 DTP10J_0:Q 0.11 NO210_1:A 0.12 G5:0 0.1*RES0 DTP10J_0:Q G5:0 0.11 NO210_1:A G5:0 0.1*END*D_NET G6 0.1*CONN*I DTP10J_1:Q O *L 0.1 *D DTP10J*I AN210_0:B I *L 0.1 *D AN210*CAP0 DTP10J_1:Q 0.11 AN210_0:B 0.12 G6:0 0.1*RES0 DTP10J_1:Q G6:0 0.11 AN210_0:B G6:0 0.1 *END*CONN*I DTP10J_0:D I *L 0.1 *D DTP10J*I NO210_0:Y O *L 0.1 *D NO210*CAP0 DTP10J_0:D 0.11 NO210_0:Y 0.12 G10:0 0.1*RES0 DTP10J_0:D G10:0 0.11 NO210_0:Y G10:0 0.1117
- Page 65 and 66: to be absolutely in complete alignm
- Page 67 and 68: In this work, we have maintained te
- Page 69 and 70: Figure 4.6 Load vs. peak power for
- Page 71 and 72: 3. The temporal correlation between
- Page 73 and 74: Each such armRepresents resistance
- Page 75 and 76: Characterized data was transformed
- Page 77 and 78: Do timing analysis and based on inp
- Page 79 and 80: of any node. Alternatively frequenc
- Page 81 and 82: Cell Char @ fix frequency(10MHz in
- Page 83 and 84: We executed the flow as explained i
- Page 85 and 86: Circuit%Drop inaverage activity%Dro
- Page 87: 4.6 SummaryWe proposed novel PG net
- Page 90 and 91: network but causing huge dynamic IR
- Page 92 and 93: Power SwitchFigure 5.2 Layout of 1M
- Page 94 and 95: power network start getting charged
- Page 96 and 97: Note that the 1 stcharacterization
- Page 98 and 99: • Maximum current surge that will
- Page 100 and 101: gates in the virtual network or mor
- Page 102 and 103: Vdesired (mV)Actual#SwitchesSwitche
- Page 104 and 105: 5.4 SummaryThere are various techni
- Page 106 and 107: 5. Power Up analysis for MTCMOS bas
- Page 108 and 109: 108
- Page 110 and 111: 21. F.N. Najm, R.Burch, P. Yang, an
- Page 112 and 113: 62. H. Mehta, R.M.Owens, M.J.Irwin,
- Page 114 and 115: 114
- Page 118 and 119: Appendix C Power Waveforms Analysis
- Page 120 and 121: Appendix E Waveform transformation
Appendix B Sample SPEF Format*SPEF "IEEE 1481-1997"*DESIGN "s27"*DATE "Mon Dec 13 10:05:00 1999"*VENDOR "TI"*PROGRAM "vlog2spef"*VERSION "1.0"*DESIGN_FLOW "Dummy From Verilog"*DIVIDER /*DELIMITER :*BUS_DELIMITER []*T_UNIT 1 NS*C_UNIT 1 PF*R_UNIT 1 KOHM*L_UNIT 1e-3 UH*PORTSG17 O *L 0.1G3 I *S 0.1 0.1G2 I *S 0.1 0.1G1 I *S 0.1 0.1G0 I *S 0.1 0.1PREZ I *S 0.1 0.1CLK I *S 0.1 0.1*D_NET G17 0.1*CONN*I IV110_1:Y O *L 0.1 *D IV110*P G17 O *L 0.1*CAP0 G17 0.11 IV110_1:Y 0.12 G17:0 0.1*RES0 G17 G17:0 0.11 IV110_1:Y G17:0 0.1*END*D_NET G3 0.1*CONN*I OR210_1:A I *L 0.1 *D OR210*P G3 I *L 0.1*CAP0 G3 0.11 OR210_1:A 0.12 G3:0 0.1*RES0 G3 G3:0 0.11 OR210_1:A G3:0 0.1*END*D_NET G2 0.1*CONN*I NO210_3:A I *L 0.1 *D NO210*P G2 I *L 0.1*CAP0 G2 0.11 NO210_3:A 0.12 G2:0 0.1*RES0 G2 G2:0 0.11 NO210_3:A G2:0 0.1*END*D_NET G1 0.1*CONN*I NO210_2:A I *L 0.1 *D NO210*P G1 I *L 0.1*CAP0 G1 0.11 NO210_2:A 0.12 G1:0 0.1*RES0 G1 G1:0 0.11 NO210_2:A G1:0 0.1*END*D_NET G0 0.1*CONN*I IV110_0:A I *L 0.1 *D IV110*P G0 I *L 0.1*CAP0 G0 0.11 IV110_0:A 0.12 G0:0 0.1*RES0 G0 G0:0 0.11 IV110_0:A G0:0 0.1*END*D_NET PREZ 0.1*CONN*I DTP10J_0:PREZ I *L 0.1 *D DTP10J*I DTP10J_1:PREZ I *L 0.1 *D DTP10J*I DTP10J_2:PREZ I *L 0.1 *D DTP10J*P PREZ I *L 0.1*CAP0 PREZ 0.11 DTP10J_0:PREZ 0.12 DTP10J_1:PREZ 0.13 DTP10J_2:PREZ 0.14 PREZ:0 0.1116
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