Power Grid Analysis in VLSI Designs - SERC
Power Grid Analysis in VLSI Designs - SERC Power Grid Analysis in VLSI Designs - SERC
62. H. Mehta, R.M.Owens, M.J.Irwin, “Energy Characterization Based on Clustering,” 33 rd Design Automation Conference, June 1996.63. D. Brooks, V. Tiwari, and M. Martonosi, “Wattch: A framework for Architectural-Level Power Analysis and Optimizations,” Proc ofInternational Symposium on Computer Architecture, pp. 83-94, June 200064. V. Tiwari, S. Malik, and A. Wolfe, ”Power Analysis of Embedded Software: A First Step toward software power minimization,” IEEETrans VLSI Systems, vol2, no. 4, pp 437-445, 199465. E. Macii, M. Pedram and F. Somenzi, “High Level Power Modeling and Estimation,” IEEE Transactions on Computer Aided Design ofIntegrated Circuits and Systems, vol 17, November 1998.66. Synopsys Prime Power - http://www.synopsys.com/products/power/primepower_ds.pdf67. Synopsys Power Compiler - http://www.synopsys.com/products/power/power_ds.pdf68. Synopsys Nanosim - http://www.synopsys.com/products/mixedsignal/nanosim/nanosim.html69. Synopsys Liberty Format - http://www.synopsys.com/partners/tapin/lib_info.html70. M Horowitz and R Gonzalez, “Energy dissipation in general purpose Microprocessors”, IJSSC, vol31, Sept 1996.71. Brglez, F. Bryan, D. Kozminski, K. , “Combinational profiles of sequential benchmark circuits”, ISCAS, vol 3, pp. 1929-1934, May1989.72. R. Wilson and D. Lammers, “Grove Calls Leakage Chip Designers’ Top Problem,” EE Times, 13 Dec 2002;www.eetimes.com/story/OEG20021213S0040.73. Intel SpeedStem technology, http://www.intel.com74. Y.Ye, S Borkar, V. De, “A New Technique for Standby Leakage Reduction in High-Performance Circuits,” 1998 Symposium on VLSICircuits, June 1998.75. M. Powell et al., “Reducing Leakage in a High Performance Deep-Submicron Instruction Cache,” IEEE Trans. VLSI, Feb 2001, pp 77-8976. Ali K., Charles H. et al., “ Effect of reverse body bias for low power CMOS circuits”77. Kaushik R, Mark C.J., Dinesh S., “leakage control with efficient use of transistor stacks in single threshold CMOS”78. Shekhar Borkar, “Low Power Design Challenges for the Decade”, 2001.79. Kumagai, K.; Iwaki, H.; Yoshida, H.; Suzuki, H.; Yamada, T.; Kurosawa, S.; “A Novel Powering Down Scheme for low Vt CMOSCircuits”, 1998 Symposium on , 11-13 June 1998. Pages:44 – 4580. Mutoh, S.; Douseki, T.; Matsuya, Y.; Aoki, T.; Yamada, J.,” 1V high-speed digital circuit technology with 0.5μm multi-thresholdCMOS”, IEEE ASIC Conference, 1993.81. Akamatsu, H.; Iwata, T.; Yamamoto, H.; Hirata, T.; Yamauchi, H.; Kotani, H.; Matsuzawa, A.; “A low power data holding circuit withan intermittent power supply scheme for sub-1V MT-CMOS LSIs”, VLSI Circuits, 1996. Digest of Technical Papers., 1996 Symposiumon , 13-15 June 1996 Pages:14 – 1582. Ye, Y.; Borkar, S.; De, V. , “A new technique for standby leakage reduction in high-performance circuits”, Symposium on VLSI Circuits,June 1998. Page(s): 40-4183. Das, K.K.; Joshi, R.V.; Chuang, C.T.; Cook, P.W.; Brown, R.B., “New digital circuit techniques for total standby leakage reduction inNano-scale SOI technology”, pp. 309-312, ISSCC, Sept 2003.84. Wenxin Wang; Anis, M.; Areibi, S, “Fast techniques for standby leakage reduction in MTCMOS circuits”, ISOCC, pp. 21-24, Sept 2004112
85. Fei Li; Lei He; Saluja, K.K.; “Estimation of maximum power-up current”, DAC, pp. 51-56, Jan 200286. Calhoun, B.H.; Honore, F.A.; Chandrakasan, A.P, “A leakage reduction methodology for distributed MTCMOS”, JSSC, pp. 818-826,May 200487. Royannez, P.; Mair, H.; Dahan, F.; Wagner, M.; Streeter, M.; Bouetel, L.; Blasquez, J.; Clasen, H.; Semino, G.; Dong, J.; Scott, D.; Pitts,B.; Raibaut, C.; Uming Ko, “90nm Low Leakage SoC Design Techniques for Wireless Applications”, ISSCC, pp. 138-139, Feb 2005.88. R. Heald, et al., “Implementation of a 3 rd Generation SPARC V9 64b Microprocessor,” Proc. IEEE ISSCC, pp 412-413, 200089. P. Gronowski, W. Bowhill, R. Preston, M. Gowan, and R. Allmon, “High Performance Microprocessor Design,” IEEE Journal of SolidState Circuits, vol 33, no 5, pp. 676-686, Apr 1998.90. J. Darnauer, D. Chengson, B. Schmidt, and E. Priest, “Electrical Evaluation of Flip-Chip package Alternatives for Next GenerationMicroprocessor,“ Electronic Components and Technology Conference, pp. 666-673, 199891. S. Borkar, “Low Power Design Challenges for the Decade,” Proc. of ISLPED, 200092. V. Tiwari, D. Singh, S. Rajgopal, G. Mehta, R. Patel and F. Baez, “Reducing Power in High performance Microprocessors,” Proc. ofDesign Automations Conference, 199793. Wachnik, R.A.; Filippi, R.G.; Shaw, T.M.; Lin, P.C, “Practical benefits of the electromigration short-length effect, including a new designrule methodology and an electromigration resistant power grid with enhanced wireability”, Sym on VLSI Technology, pp. 220-221, June2000.94. J. Kitchin, “Statistical Electromigration Budgeting for Reliable Design and Verification in a 300-MHz Microprocessor”, Symposium onVLSI Circuits Digests, pp. 115-116, 199595. T .H. Cormen, C. E. Leiserson, R. L. Rivest “Introduction to Algorithms”, PHI96. Chapra, S.C, Canale R P “Numerical Methods for Engineers” 3rd Ed., McGraw-Hill 1998.97. Rabey, “Digital Integrated Circuits Design”, Pearson Education, Second Edition, 2003113
- Page 61 and 62: We can approximate the average powe
- Page 63 and 64: 4 Power Supply Noise Analysis4.1 Ov
- Page 65 and 66: to be absolutely in complete alignm
- Page 67 and 68: In this work, we have maintained te
- Page 69 and 70: Figure 4.6 Load vs. peak power for
- Page 71 and 72: 3. The temporal correlation between
- Page 73 and 74: Each such armRepresents resistance
- Page 75 and 76: Characterized data was transformed
- Page 77 and 78: Do timing analysis and based on inp
- Page 79 and 80: of any node. Alternatively frequenc
- Page 81 and 82: Cell Char @ fix frequency(10MHz in
- Page 83 and 84: We executed the flow as explained i
- Page 85 and 86: Circuit%Drop inaverage activity%Dro
- Page 87: 4.6 SummaryWe proposed novel PG net
- Page 90 and 91: network but causing huge dynamic IR
- Page 92 and 93: Power SwitchFigure 5.2 Layout of 1M
- Page 94 and 95: power network start getting charged
- Page 96 and 97: Note that the 1 stcharacterization
- Page 98 and 99: • Maximum current surge that will
- Page 100 and 101: gates in the virtual network or mor
- Page 102 and 103: Vdesired (mV)Actual#SwitchesSwitche
- Page 104 and 105: 5.4 SummaryThere are various techni
- Page 106 and 107: 5. Power Up analysis for MTCMOS bas
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- Page 110 and 111: 21. F.N. Najm, R.Burch, P. Yang, an
- Page 114 and 115: 114
- Page 116 and 117: Appendix B Sample SPEF Format*SPEF
- Page 118 and 119: Appendix C Power Waveforms Analysis
- Page 120 and 121: Appendix E Waveform transformation
62. H. Mehta, R.M.Owens, M.J.Irw<strong>in</strong>, “Energy Characterization Based on Cluster<strong>in</strong>g,” 33 rd Design Automation Conference, June 1996.63. D. Brooks, V. Tiwari, and M. Martonosi, “Wattch: A framework for Architectural-Level <strong>Power</strong> <strong>Analysis</strong> and Optimizations,” Proc ofInternational Symposium on Computer Architecture, pp. 83-94, June 200064. V. Tiwari, S. Malik, and A. Wolfe, ”<strong>Power</strong> <strong>Analysis</strong> of Embedded Software: A First Step toward software power m<strong>in</strong>imization,” IEEETrans <strong>VLSI</strong> Systems, vol2, no. 4, pp 437-445, 199465. E. Macii, M. Pedram and F. Somenzi, “High Level <strong>Power</strong> Model<strong>in</strong>g and Estimation,” IEEE Transactions on Computer Aided Design ofIntegrated Circuits and Systems, vol 17, November 1998.66. Synopsys Prime <strong>Power</strong> - http://www.synopsys.com/products/power/primepower_ds.pdf67. Synopsys <strong>Power</strong> Compiler - http://www.synopsys.com/products/power/power_ds.pdf68. Synopsys Nanosim - http://www.synopsys.com/products/mixedsignal/nanosim/nanosim.html69. Synopsys Liberty Format - http://www.synopsys.com/partners/tap<strong>in</strong>/lib_<strong>in</strong>fo.html70. M Horowitz and R Gonzalez, “Energy dissipation <strong>in</strong> general purpose Microprocessors”, IJSSC, vol31, Sept 1996.71. Brglez, F. Bryan, D. Kozm<strong>in</strong>ski, K. , “Comb<strong>in</strong>ational profiles of sequential benchmark circuits”, ISCAS, vol 3, pp. 1929-1934, May1989.72. R. Wilson and D. Lammers, “Grove Calls Leakage Chip Designers’ Top Problem,” EE Times, 13 Dec 2002;www.eetimes.com/story/OEG20021213S0040.73. Intel SpeedStem technology, http://www.<strong>in</strong>tel.com74. Y.Ye, S Borkar, V. De, “A New Technique for Standby Leakage Reduction <strong>in</strong> High-Performance Circuits,” 1998 Symposium on <strong>VLSI</strong>Circuits, June 1998.75. M. Powell et al., “Reduc<strong>in</strong>g Leakage <strong>in</strong> a High Performance Deep-Submicron Instruction Cache,” IEEE Trans. <strong>VLSI</strong>, Feb 2001, pp 77-8976. Ali K., Charles H. et al., “ Effect of reverse body bias for low power CMOS circuits”77. Kaushik R, Mark C.J., D<strong>in</strong>esh S., “leakage control with efficient use of transistor stacks <strong>in</strong> s<strong>in</strong>gle threshold CMOS”78. Shekhar Borkar, “Low <strong>Power</strong> Design Challenges for the Decade”, 2001.79. Kumagai, K.; Iwaki, H.; Yoshida, H.; Suzuki, H.; Yamada, T.; Kurosawa, S.; “A Novel <strong>Power</strong><strong>in</strong>g Down Scheme for low Vt CMOSCircuits”, 1998 Symposium on , 11-13 June 1998. Pages:44 – 4580. Mutoh, S.; Douseki, T.; Matsuya, Y.; Aoki, T.; Yamada, J.,” 1V high-speed digital circuit technology with 0.5μm multi-thresholdCMOS”, IEEE ASIC Conference, 1993.81. Akamatsu, H.; Iwata, T.; Yamamoto, H.; Hirata, T.; Yamauchi, H.; Kotani, H.; Matsuzawa, A.; “A low power data hold<strong>in</strong>g circuit withan <strong>in</strong>termittent power supply scheme for sub-1V MT-CMOS LSIs”, <strong>VLSI</strong> Circuits, 1996. Digest of Technical Papers., 1996 Symposiumon , 13-15 June 1996 Pages:14 – 1582. Ye, Y.; Borkar, S.; De, V. , “A new technique for standby leakage reduction <strong>in</strong> high-performance circuits”, Symposium on <strong>VLSI</strong> Circuits,June 1998. Page(s): 40-4183. Das, K.K.; Joshi, R.V.; Chuang, C.T.; Cook, P.W.; Brown, R.B., “New digital circuit techniques for total standby leakage reduction <strong>in</strong>Nano-scale SOI technology”, pp. 309-312, ISSCC, Sept 2003.84. Wenx<strong>in</strong> Wang; Anis, M.; Areibi, S, “Fast techniques for standby leakage reduction <strong>in</strong> MTCMOS circuits”, ISOCC, pp. 21-24, Sept 2004112
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