Power Grid Analysis in VLSI Designs - SERC
Power Grid Analysis in VLSI Designs - SERC Power Grid Analysis in VLSI Designs - SERC
21. F.N. Najm, R.Burch, P. Yang, and I.N. Hajj. “Probabilistic Simulation for Reliability Analysis of CMOS VLSI Circuits”. IEEETransactions on CAD, 9(4):439-450, April 1990.22. Randal S and Tom Phoenix and Brian d foy, “Learning Perl”, 4 th Edition, O’Reilly & Associates, ISBN 059610105823. Matlab Tutorial, http://www.math.ufl.edu/help/matlab-tutorial/24. Synopsys, Inc, “Using the Synopsys® Design Constraints Format”, Application Note, Sept 2005.25. Himanshu Bhatnagar, “Advanced ASIC Chip Synthesis: Using Synopsys Design Compiler Physical Compiler and Primetime”, 2 ndEdition, Kluwer Academic Publishers, ISBN: 0792376447.26. Martin Saint-Laurent, Swaminathan, "Impact of Power Supply Noise on Timing In High Frequency Microprocessors", IEEE Trans onAdvanced Packaging, pp. 135-144, Feb 200427. Kriplani, H.; Najm, F.; Hajj, I, “Improved Delay and Current Models for Estimating Maximum Currents in CMOS VLSI Circuits”,ISCAS 94, pp. 435-438, June 1994.28. Kriplani, H.; Najm, F.N.; Hajj, I.N, “Pattern Independent Maximum Current Estimation in Power and Ground Buses of CMOS VLSICircuits: Algorithms, Signal Correlations, and Their Resolution”, IEEE Trans on CAD of international circuits and systems, pp. 998-1012, Aug 1995.29. Hsiao, M.S.; Rudnick, E.M.; Patel, J.H., “Peak Power Estimation of VLSI Circuits: New Peak Power Measures”, IEEE Trans on VLSISystems, pp. 435-439, Aug 200030. Qing Wu; Qinru Qiu; Pedram, M, “Estimation of Peak Power Dissipation in VLSI Circuits Using the Limiting Distributions of ExtremeOrder Statistics”, IEEE Trans on CAD of integrated Circuits and Systems, pp. 942-956, Aug 2001.31. Boliolo, A. Benini, L. de Micheli, G. Ricco, B., “Gate-level power and current simulation of CMOS integrated circuits”, Very LargeScale Integration (VLSI) Systems, pp. 473-488, Dec 199732. Anantha Chandrakasan’s Home Page: http://www-mtl.mit.edu/~anantha/publications.html,http://www.fetchbook.info/search_Anantha_Chandrakasan/searchBy_Author.html33. FFT Tutorial, http://www.ele.uri.edu/~hansenj/projects/ele436/fft.pdf34. Jeff Tranter and Paul Raines, “Tcl/Tk in Nutshell”, O’Reilly Associates, ISBN 156592433935. Alan V. Oppenheim, Ronald W. Schafer, John R. Buck, “Discrete Time Signal Processing“, 2 nd Edition, Prentice Hall, ISBN 013754920236. Chen, H.H.; Ling, D.D, “Power Supply Analysis Methodology for Deep-Submicron VLSI Chip Design”, DAC, pp. 638-643, June 1997.37. Yi-Shing Chang; Gupta, S.K.; Breuer, M.A, “Analysis of Ground Bounce in Deep-Submicron Circuits”, VLSI Test Symposium, pp. 110-116, May 199738. Yi-Min Jiang; Kwang-Ting Cheng; An-Chang Deng, “Estimation of Maximum Power Supply Noise for Deep Sub-Micron Designs”,International sym on low power electronics and design, pp. 233-238, Aug 1998.39. Zhao, S.; Roy, K.; Koh, C.-K, “Estimation of Inductive and Resistive Switching Noise on Power Supply Network in Deep Sub-MicronCMOS Circuits”, International conference on Computer Design, pp. 65-72, Sept 2000.40. S. Bobba, I.N.Hajj, “Maximum voltage variation in the power distribution network of VLSI circuits with RLC Models,” Proc of ISLPED,Aug2001110
41. Bai, G.; Bobba, S.; Hajji, I.N, "Static Timing Analysis Including Power Supply Noise Effect on Propagation Delay in VLSI Circuits",DAC, pp. 295-300, 2001.42. G. Steele, et al., “Full-Chip Verification Methods for DSM Power Distribution Systems,” Proc. Of DAC, pp. 744-749, 199843. R. Chaudhry, D. Blaauw, R. Panda and T. Edwards, “Current Signature Compression For IR-Drop Analysis,” Proc. Design AutomationConference, pp. 162-167, 200044. S. Bobba and I. N. Hajj, “Estimation of maximum current envelope for power bus analysis and design,” Proc. of ISPD, pp 141-146, Apr199845. Rishi Bhooshan (TI) et.al, “A Unique Method For Dynamic Voltage Drop Analysis and Decoupling Capacitance Estimation,, VDAT200346. Cirit, M.A., “Characterizing a VLSI standard cell library”, Digital Object Identifier 10.1109/CICC, pp.25.7.2-25.7.4, May 199147. Debnath, S.P.; Sukumar, J.; Udaykumar, H, “A methodology for fast vector based power supply and substrate noise analyses”,International conference on VLSI Design, pp. 808-811, Jan 2005.48. Dalal, A.; Lev, L.; Mitra, S.; “Design of an efficient power distribution network for the UltraSPARC-I microprocessor”, IEEE conferenceon Computer Design: VLSI in computers and processors, pp. 118-123, Oct 199549. Chen, H.H.; Schuster, S.E.; „On-chip decoupling capacitor optimization for high-performance VLSI design”, VLSI Technology, Systemsand Applications, pp. 99-103, June 1995.50. Larsson, P, “Power supply noise in future IC's: a crystal ball reading”, Custom Integrated Circuits, pp. 467-474, May 1999.51. Sotman, M.; Popovich, M.; Kolodny, A.; Friedman, E, “Leveraging symbiotic on-die decoupling capacitance”, Electrical Performance ofElectronic Packaging, pp. 111-114, Oct 200552. Larsson, P, “Resonance and damping in CMOS circuits with on-chip decoupling capacitance”, IEEE Transactions on Circuits andSystems-I, vol 45, pp. 849-858, Aug 199853. Larsson, P, “Parasitic Resistance in an MOS Transistor Used as On-Chip Decoupling Capacitance,” IEEE Journal of Solid State Circuits,vol 32, pp 574-576, Apr 199754. Chaudhry, R.; Panda, R.; Edwards, T.; Blaauw, D, “Design and analysis of power distribution networks with accurate RLC models”,International conference on VLSI Design, pp. 151-155, Jan 200055. Min Zhao; Panda, R.V.; Sapatnekar, S.S.; Edwards, T.; Chaudhry, R.; Blaauw, D, “Hierarchical analysis of power distribution networks”,DAC, pp. 150-155, June 200056. IBM Methodology for Power Supply Noise - http://www.research.ibm.com/da/nova.html57. R. Heald et. al, “Implementation of a 3 rd Generation Sparc V9 64b Microprocessor”, Proc IEEE ISSCC, pp. 412-413, 200058. Yi-Min Jiang Kwang-Ting Cheng, “Analysis of Performance Impact Caused by Power Supply Noise in Deep Submicron Devices”, DAC,June 199959. Apache Design Solutions, “Reshaping Nanometer Flows with Physical Power Integrity”, http://www.apache-da.com, White Paper, May2003.60. Anthony Ralston, Philip Rabinowitz, “A First course in Numerical Analysis”, 2 nd Edition, Dover Publications, ISBN 048641454X.61. Kalpesh Shah, “SNUG 2006 Panel Discussion”111
- Page 59 and 60: DesignNamePowerCompilerProposedAppr
- Page 61 and 62: We can approximate the average powe
- Page 63 and 64: 4 Power Supply Noise Analysis4.1 Ov
- Page 65 and 66: to be absolutely in complete alignm
- Page 67 and 68: In this work, we have maintained te
- Page 69 and 70: Figure 4.6 Load vs. peak power for
- Page 71 and 72: 3. The temporal correlation between
- Page 73 and 74: Each such armRepresents resistance
- Page 75 and 76: Characterized data was transformed
- Page 77 and 78: Do timing analysis and based on inp
- Page 79 and 80: of any node. Alternatively frequenc
- Page 81 and 82: Cell Char @ fix frequency(10MHz in
- Page 83 and 84: We executed the flow as explained i
- Page 85 and 86: Circuit%Drop inaverage activity%Dro
- Page 87: 4.6 SummaryWe proposed novel PG net
- Page 90 and 91: network but causing huge dynamic IR
- Page 92 and 93: Power SwitchFigure 5.2 Layout of 1M
- Page 94 and 95: power network start getting charged
- Page 96 and 97: Note that the 1 stcharacterization
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- Page 100 and 101: gates in the virtual network or mor
- Page 102 and 103: Vdesired (mV)Actual#SwitchesSwitche
- Page 104 and 105: 5.4 SummaryThere are various techni
- Page 106 and 107: 5. Power Up analysis for MTCMOS bas
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- Page 112 and 113: 62. H. Mehta, R.M.Owens, M.J.Irwin,
- Page 114 and 115: 114
- Page 116 and 117: Appendix B Sample SPEF Format*SPEF
- Page 118 and 119: Appendix C Power Waveforms Analysis
- Page 120 and 121: Appendix E Waveform transformation
21. F.N. Najm, R.Burch, P. Yang, and I.N. Hajj. “Probabilistic Simulation for Reliability <strong>Analysis</strong> of CMOS <strong>VLSI</strong> Circuits”. IEEETransactions on CAD, 9(4):439-450, April 1990.22. Randal S and Tom Phoenix and Brian d foy, “Learn<strong>in</strong>g Perl”, 4 th Edition, O’Reilly & Associates, ISBN 059610105823. Matlab Tutorial, http://www.math.ufl.edu/help/matlab-tutorial/24. Synopsys, Inc, “Us<strong>in</strong>g the Synopsys® Design Constra<strong>in</strong>ts Format”, Application Note, Sept 2005.25. Himanshu Bhatnagar, “Advanced ASIC Chip Synthesis: Us<strong>in</strong>g Synopsys Design Compiler Physical Compiler and Primetime”, 2 ndEdition, Kluwer Academic Publishers, ISBN: 0792376447.26. Mart<strong>in</strong> Sa<strong>in</strong>t-Laurent, Swam<strong>in</strong>athan, "Impact of <strong>Power</strong> Supply Noise on Tim<strong>in</strong>g In High Frequency Microprocessors", IEEE Trans onAdvanced Packag<strong>in</strong>g, pp. 135-144, Feb 200427. Kriplani, H.; Najm, F.; Hajj, I, “Improved Delay and Current Models for Estimat<strong>in</strong>g Maximum Currents <strong>in</strong> CMOS <strong>VLSI</strong> Circuits”,ISCAS 94, pp. 435-438, June 1994.28. Kriplani, H.; Najm, F.N.; Hajj, I.N, “Pattern Independent Maximum Current Estimation <strong>in</strong> <strong>Power</strong> and Ground Buses of CMOS <strong>VLSI</strong>Circuits: Algorithms, Signal Correlations, and Their Resolution”, IEEE Trans on CAD of <strong>in</strong>ternational circuits and systems, pp. 998-1012, Aug 1995.29. Hsiao, M.S.; Rudnick, E.M.; Patel, J.H., “Peak <strong>Power</strong> Estimation of <strong>VLSI</strong> Circuits: New Peak <strong>Power</strong> Measures”, IEEE Trans on <strong>VLSI</strong>Systems, pp. 435-439, Aug 200030. Q<strong>in</strong>g Wu; Q<strong>in</strong>ru Qiu; Pedram, M, “Estimation of Peak <strong>Power</strong> Dissipation <strong>in</strong> <strong>VLSI</strong> Circuits Us<strong>in</strong>g the Limit<strong>in</strong>g Distributions of ExtremeOrder Statistics”, IEEE Trans on CAD of <strong>in</strong>tegrated Circuits and Systems, pp. 942-956, Aug 2001.31. Boliolo, A. Ben<strong>in</strong>i, L. de Micheli, G. Ricco, B., “Gate-level power and current simulation of CMOS <strong>in</strong>tegrated circuits”, Very LargeScale Integration (<strong>VLSI</strong>) Systems, pp. 473-488, Dec 199732. Anantha Chandrakasan’s Home Page: http://www-mtl.mit.edu/~anantha/publications.html,http://www.fetchbook.<strong>in</strong>fo/search_Anantha_Chandrakasan/searchBy_Author.html33. FFT Tutorial, http://www.ele.uri.edu/~hansenj/projects/ele436/fft.pdf34. Jeff Tranter and Paul Ra<strong>in</strong>es, “Tcl/Tk <strong>in</strong> Nutshell”, O’Reilly Associates, ISBN 156592433935. Alan V. Oppenheim, Ronald W. Schafer, John R. Buck, “Discrete Time Signal Process<strong>in</strong>g“, 2 nd Edition, Prentice Hall, ISBN 013754920236. Chen, H.H.; L<strong>in</strong>g, D.D, “<strong>Power</strong> Supply <strong>Analysis</strong> Methodology for Deep-Submicron <strong>VLSI</strong> Chip Design”, DAC, pp. 638-643, June 1997.37. Yi-Sh<strong>in</strong>g Chang; Gupta, S.K.; Breuer, M.A, “<strong>Analysis</strong> of Ground Bounce <strong>in</strong> Deep-Submicron Circuits”, <strong>VLSI</strong> Test Symposium, pp. 110-116, May 199738. Yi-M<strong>in</strong> Jiang; Kwang-T<strong>in</strong>g Cheng; An-Chang Deng, “Estimation of Maximum <strong>Power</strong> Supply Noise for Deep Sub-Micron <strong>Designs</strong>”,International sym on low power electronics and design, pp. 233-238, Aug 1998.39. Zhao, S.; Roy, K.; Koh, C.-K, “Estimation of Inductive and Resistive Switch<strong>in</strong>g Noise on <strong>Power</strong> Supply Network <strong>in</strong> Deep Sub-MicronCMOS Circuits”, International conference on Computer Design, pp. 65-72, Sept 2000.40. S. Bobba, I.N.Hajj, “Maximum voltage variation <strong>in</strong> the power distribution network of <strong>VLSI</strong> circuits with RLC Models,” Proc of ISLPED,Aug2001110
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