Power Grid Analysis in VLSI Designs - SERC

AbstractPower has become an important design closure parameter in today’s ultra low submicrondigital designs. The impact of the increase in power is multi-discipline to researchers rangingfrom power supply design, power converters or voltage regulators design, system, board andpackage thermal analysis, power grid design and signal integrity analysis to minimizing poweritself. This work focuses on challenges arising due to increase in power to power grid designand analysis.Challenges arising due to lower geometries and higher power are very well researched topicsand there is still lot of scope to continue work. Traditionally, designs go through average IRdrop analysis. Average IR drop analysis is highly dependent on current dissipation estimation.This work proposes a vector less probabilistic toggle estimation which is extension of one ofthe approaches proposed in literature. We have further used toggles computed using thisapproach to estimate power of ISCAS89 benchmark circuits. This provides insight into qualityof toggles being generated. Power Estimation work is further extended to comprehend withvarious state of the art methodologies available i.e. spice based power estimation, logicsimulation based power estimation, commercially available tool comparisons etc. We finallyarrived at optimum flow recommendation which can be used as per design need and schedule.Today’s design complexity – high frequencies, high logic densities and multiple level clock andpower gating - has forced design community to look beyond average IR drop. High rate ofswitching activities induce power supply fluctuations to cells in design which is known as11