Power Grid Analysis in VLSI Designs - SERC

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5. Power Up analysis for MTCMOS based digital designs. The methodology is validatedusing prototype flow and gives superlative run time improvement compare to Spice.The methodology also helps in MTCMOS gate optimization.6.2 Scope of Future WorkAnalysis approaches proposed in this work helps in robust power grid analysis. The work hassome extensions possible to further help designs.First, power estimation proposed in this work relies on gate level netlist. An RTL level powerestimation helps block designer to trade off power early in the design like MTCMOS usage ormulti-Vt usage as proposed in [17].Second, it is possible to improve pre-layout and post layout power number correlation. One ofthe reasons for them to be different is clock tree expansion and buffer insertion while doingplacement and routing in design to meet timing constraints. Early estimation techniques can bedeveloped to estimate additional cell count to better correlate power numbers in various stages.Third, the amount of cell characterization data stored for each cell is very huge. A typical ASICtechnology contains 2000-4000 cells. This data reduction is possible if we can just store thecurrent signatures during transition and use that to model current source in block level analysis.This will also eliminate the need of frequency domain transform being performed here.Techniques used in some of the commercial tools in conjunction with the analysis approachpresented in this work can help improving data reduction.Fourth, we have not got into details of decoupling capacitance for instantaneous IR dropanalysis in this work. It is possible to further extend the work to extensively study various106
decoupling capacitors – intrinsic due to NWELL, non switching gates, RAMs as well asintentional being distributed by user. Decoupling capacitor estimation, characterization andwhat-if impact analysis on instantaneous IR drop is import area for further research.Fifth MTCMOS analysis approach proposed in this work is useful early in design planning tomake efficient tradeoffs of MTCMOS switches vs. noise tolerance levels in design. In this work,we have modeled switch power network with a lumped capacitance. This does not model timedomain behavior of PG network due to PG resistance. A more accurate approach can bedeveloped that models distributed RC for PG network once placement and power routing isdone. It is our belief that this will give quick accurate analysis of actual network compare toSPICE like simulations.107
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Power Grid Analysis in VLSI Designs
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4.4.1 Timing Information Generation
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Figure 3 1GHz, Peak: 838.2 uW......
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AbstractPower has become an importa
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1 Introduction1.1 MotivationVLSI in
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Further, Figure 1.3 shows that ther
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proposed in a few papers. In this t
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• Degradation in switching speeds
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Second, today’s design has huge P
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Figure 1.6 Total power break up int
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CMOSDieAcronym for Complimentary Me
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2 Toggle Activity Estimation2.1 Ove
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For large T, D(x) becomes time inva
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done hierarchically or there is reu
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A Sample SDC file with above comman
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Some of the care needs to be taken
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Figure 2.5 Timing Arcs in extracted
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3 Power Estimation3.1 OverviewAccur
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In this work, above power component
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on the required accuracy, different
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Based on power sensitivity and tool
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with SPICE. Power Mill is dynamic s
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DREPGENDREPFILE+ DATAGENFUNCTDLRAND
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3.4.3 Interconnect setupAll the cir
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DesignNameIN OUT Flops Boolean(gate
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Page 57 and 58: Design Name CLK Power Total Power %
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Page 73 and 74: Each such armRepresents resistance
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Page 92 and 93: Power SwitchFigure 5.2 Layout of 1M
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Page 96 and 97: Note that the 1 stcharacterization
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Page 104 and 105: 5.4 SummaryThere are various techni
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Page 110 and 111: 21. F.N. Najm, R.Burch, P. Yang, an
Page 112 and 113: 62. H. Mehta, R.M.Owens, M.J.Irwin,
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Page 116 and 117: Appendix B Sample SPEF Format*SPEF
Page 118 and 119: Appendix C Power Waveforms Analysis
Page 120 and 121: Appendix E Waveform transformation
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