Power Grid Analysis in VLSI Designs - SERC

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5.4 SummaryThere are various techniques to improve leakage power of the design - ‘gated power supply’ or‘sleep transistor’ or ‘switched power network’ is one of the efficient methods to reduce theleakage power. The analysis techniques described in this work helps in giving quick data forarchitecture level decisions while using ‘switched network’ technique. The runtime is in fewseconds and hence Design Team can do lots of iterations to get the optimum number ofswitches. The analytical method to calculate total no of switches is fast since it involves onetime SPICE simulation – only IV characteristic of switch - and rest of the analysis is performedusing static analysis. We have also analyzed ‘power on glitch’ for the design using the methodthat contributes to Power Supply Noise during power up. All the results are closely matchingwith SPICE simulation.104
6 Conclusion6.1 SummaryPower Grid analysis challenges being faced by CMOS technology is discussed in this thesis.For robust power grid, designs need to go through following analysis:• Accurate Power Estimation• Instantaneous IR drop analysis and decap planning• Power Up analysis for designs using MTCMOS for leakage reductionThe key results of this work can be summarized as follows:1. Successfully implemented hierarchical probabilistic toggle computation approach that isapplicable to multi-million gate designs maintaining the desired accuracy2. Power Dissipation in cell based CMOS design discussed. A flow is proposed to dopower estimation in various design stages that can improve the accuracy of estimation.The flow also helps user to make run time and accuracy tradeoffs3. Proposed the cell characterization methodology for instantaneous IR drop analysis aswell as Power Up analysis for MTCMOS4. Discussed a prototype flow developed for instantaneous IR drop estimation based onaverage toggle rate computed by the proposed toggle methodology in this work. Thisflow estimates instantaneous as well as average IR drop numbers during samesimulation.105
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Power Grid Analysis in VLSI Designs
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4.4.1 Timing Information Generation
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Figure 3 1GHz, Peak: 838.2 uW......
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AbstractPower has become an importa
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1 Introduction1.1 MotivationVLSI in
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Further, Figure 1.3 shows that ther
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proposed in a few papers. In this t
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• Degradation in switching speeds
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Second, today’s design has huge P
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Figure 1.6 Total power break up int
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CMOSDieAcronym for Complimentary Me
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2 Toggle Activity Estimation2.1 Ove
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For large T, D(x) becomes time inva
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done hierarchically or there is reu
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A Sample SDC file with above comman
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Some of the care needs to be taken
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Figure 2.5 Timing Arcs in extracted
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3 Power Estimation3.1 OverviewAccur
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In this work, above power component
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on the required accuracy, different
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Based on power sensitivity and tool
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with SPICE. Power Mill is dynamic s
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DREPGENDREPFILE+ DATAGENFUNCTDLRAND
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3.4.3 Interconnect setupAll the cir
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Page 57 and 58: Design Name CLK Power Total Power %
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Page 110 and 111: 21. F.N. Najm, R.Burch, P. Yang, an
Page 112 and 113: 62. H. Mehta, R.M.Owens, M.J.Irwin,
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Page 116 and 117: Appendix B Sample SPEF Format*SPEF
Page 118 and 119: Appendix C Power Waveforms Analysis
Page 120 and 121: Appendix E Waveform transformation
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Power Grid Analysis in VLSI Designs - SERC

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