Power Grid Analysis in VLSI Designs - SERC
Power Grid Analysis in VLSI Designs - SERC
Power Grid Analysis in VLSI Designs - SERC
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5.4 SummaryThere are various techniques to improve leakage power of the design - ‘gated power supply’ or‘sleep transistor’ or ‘switched power network’ is one of the efficient methods to reduce theleakage power. The analysis techniques described <strong>in</strong> this work helps <strong>in</strong> giv<strong>in</strong>g quick data forarchitecture level decisions while us<strong>in</strong>g ‘switched network’ technique. The runtime is <strong>in</strong> fewseconds and hence Design Team can do lots of iterations to get the optimum number ofswitches. The analytical method to calculate total no of switches is fast s<strong>in</strong>ce it <strong>in</strong>volves onetime SPICE simulation – only IV characteristic of switch - and rest of the analysis is performedus<strong>in</strong>g static analysis. We have also analyzed ‘power on glitch’ for the design us<strong>in</strong>g the methodthat contributes to <strong>Power</strong> Supply Noise dur<strong>in</strong>g power up. All the results are closely match<strong>in</strong>gwith SPICE simulation.104