Xilinx XAPP713 Virtex-4 RocketIO Bit-Error Rate Tester, application ...

Data Plane DescriptionRTable 2: MGT Data Width and Encoding Options in XBERT Reference DesignMGT Fabric Interface Width(XBERT Data Width)The reference design produces standard PRBS patterns in the serial data stream. In order totransmit and receive raw PRBS patterns, the 8B/10B or 64B/66B coding on a Virtex-4 MGTshould be bypassed. Such raw PRBS patterns are considered to be most stressful to the MGTon both run length and DC balance aspects. When 8B/10B is enabled, the run length oftransmission pattern is limited to a maximum 5 bits. The 8B/10B encoder and decoder alsorequire the use of comma detection and alignment in the MGT.Depending on the target line rate, the reference design supports using the analog CDR or thedigital oversampled receiver in the MGT.MGT Clocking SchemeMGT InternalData WidthEncoding/Decoding16 32 None16 40 8B/10B20 40 None32 32 None32 40 8B/10B40 40 NoneFigure 2 shows the distribution of MGT reference clocks in Virtex-4 FPGA for a typical4-channel XBERT implementation.Channel 2 Channel 3REFCLK2_LEFT_PREFCLK2_LEFT_NGT11CLK_MGT_LEFT_2REFCLK1GT11_AREFCLK2GREFCLKREFCLK1GT11_AREFCLK2GREFCLKGT11CLK_MGT_RIGHT_2REFCLK2_RIGHT_PREFCLK2_RIGHT_NREFCLK1GT11_BREFCLK2GREFCLKREFCLK1GT11_BREFCLK2GREFCLKSYNCLK2SYNCLK1Channel 0 Channel 1REFCLK1GT11_AREFCLK2REFCLK1GT11_AREFCLK2SYNCLK1SYNCLK2REFCLK1_LEFT_PREFCLK1_LEFT_NGT11CLK_MGT_LEFT_1GREFCLKREFCLK1GT11_BREFCLK2GREFCLKREFCLK1GT11_BREFCLK2GT11CLK_MGT_RIGHT_1REFCLK1_RIGHT_PREFCLK1_RIGHT_NGREFCLKGREFCLKBUFGIBUFGDSGREFCLK_P GREFCLK_NFigure 2: MGT Reference Clock Distribution in XBERT Reference Designwww.BDTIC.com/XILINXX713_02_081505XAPP713 (v1.1) April 18, 2007 www.xilinx.com 4