Xilinx XAPP713 Virtex-4 RocketIO Bit-Error Rate Tester, application ...

Multi-Channel XBERT ModuleRTable 9: Definitions of the 26-bit Control Vector (GPIO_IN[6:31]) (Continued)Address Bit Name Description12[6:21] DI[22:29] DADDR30 DWE31 DEN[6:7] N/A Reserved[8:23] FRAME_LEN24 N/A Reserved25 EN_8B10B[26:29] PAT_ID30 FRAMED31 COMMA_ALIGN_ENABLEData to write to the DRP bus on the selected MGT inthe selected channel.Sets the address for DRP read or write on theselected MGT in the selected channel.Selects DRP write or read operation on the selectedMGT in the selected channel.0: DRP read1: DRP writeRising edge of this signal enables DRP bus toperform a single read/write operation on the selectedMGT in the selected channel.Sets the frame length of a delimited pattern in aframed transmission on both MGTs in the selectedchannel.The length of a frame begins from the first wordfollowing an inter-frame-gap (IFG) and ends at thelast word prior to the next IFG. The length of a framecan be from one word to 65,535 words.Enable 8B/10B encoding/decoding on both MGTs inthe selected channel.Selects a pattern to generate on TX and verify on RXof both MGTs in the selected channel.Refer to Table 3, page 8 for a list of supportedpatternsEnable the framed transmission on both MGTs in theselected channel.This function delimits the output data with idlepattern.Enable the comma alignment on both MGTs in theselected channel.This function requires the presence of idle pattern inthe received data.www.BDTIC.com/XILINXXAPP713 (v1.1) April 18, 2007 www.xilinx.com 21