Xilinx XAPP713 Virtex-4 RocketIO Bit-Error Rate Tester, application ...

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Multi-Channel XBERT ModuleRTable 6: Interface Signals of the Multi-Channel XBERT Module (Continued)RXP[c * 2–1:0],RXN[c * 2 – 1:0]TXOUTCLK1_OUT[c * 2 – 1:0]RXRECCLK1_OUT[c * 2 – 1:0]TXOUTCLK2_OUT[c * 2 – 1:0]RXRECCLK2_OUT[c * 2 – 1:0]LEDS[19:0]HEADERS[4:0]SUPERCLK_CTRL[8:0]Name Direction DescriptionInputOutputOutputOutputOutputOutputOutputOutputNotes:1. c is the number of channels implemented in the XBERT reference design.MGT differential ports that receive serial data.Each Channel inputs two bits as follows: Bit 0is the input of MGTA in the channel. Bit 1 isthe input of MGTB in the channel.Non-buffered TXOUTCLK1 outputs fromevery MGTs implemented in the design. Eachchannel outputs two bits as follows: Bit 0 isthe output of MGTA in the channel, and Bit 1is the output of MGTB in the channel.Non-buffered RXRECCLK1 outputs fromevery MGT implemented in the design. Eachchannel outputs two bits as follows: Bit 0 isthe output of MGTA in the channel, and Bit 1is the output of MGTB in the channel.Non-buffered TXOUTCLK2 outputs fromevery MGTs implemented in the design. Eachchannel outputs two bits as follows: Bit 0 isthe output of MGTA in the channel, and Bit 1is the output of MGTB in the channel.Non-buffered RXRECCLK2 outputs fromevery MGT implemented in the design. Eachchannel outputs two bits as follows: Bit 0 isthe output of MGTA in the channel, and Bit 1is the output of MGTB in the channel.Bits 9 to 0 indicate the link status of all MGTsimplemented on the left side. Bits 1 and 0correspond to the MGTB and MGTA withinchannel 0. Bits 9 and 8 correspond to theMGTB and MGTA within channel 8.Bits 19 to 10 indicate the link status of allMGTs implemented on the right side. Bits 11and 10 correspond to the MGTB and MGTAwithin channel 1. Bits 19 and 18 correspondto the MGTB and MGTA within channel 9.Bit 0 is the SYSCLK. Bit 1 is the GREFCLK[0].Bits 2 to 4 are unused.Optional control outputs to the SuperClockmodule used in Xilinx ML42x platform.Table 7 and Table 8 list the bit definitions of the 32-bit GPIO input (GPIO_IN) and GPIO output(GPIO_OUT) registers, respectively.www.BDTIC.com/XILINXXAPP713 (v1.1) April 18, 2007 www.xilinx.com 18
Multi-Channel XBERT ModuleRTable 7: Bit Definitions of the 32-bit GPIO Input (GPIO_IN[0:31])Bit Vector Name Description[0:1] OPCODEOperation Code.0b11: GPIO write operation. GPIO_IN carries a controlvector (CTRL) at the current cycle. The address of thiscontrol vector is set by ADDR at the current cycle.0b01: GPIO read operation. GPIO_OUT carries a statusvector (STAT) at the next cycle. The address of thisstatus vector is set by ADDR at the current cycle.Others: Reserved[2:4] ADDR Address of the control or status vector.[5] N/A Reserved.[6:31] CTRL26-bit control vector transferred from the microprocessor to thedata plane (the XBERT module). See Table 9 for bit definitions ofthis vector.Table 8: Bit Definitions of the 32-bit GPIO Output (GPIO_OUT[0:31])Bit Vector Name Description[0:31] STAT32-bit status vector transferred from the data plane (the XBERTmodule) to the microprocessor.Table 9 defines the bits of the 26-bit control vector (CTRL) at various addresses. Table 10defines the bits of the 32-bit status vector (STAT) at various addresses. Note that some ofcontrol and status vectors are dedicated to each MGT in a channel, while others are shared byboth MGTs (MGTA and MGTB) in a channel.www.BDTIC.com/XILINXXAPP713 (v1.1) April 18, 2007 www.xilinx.com 19
Page 1 and 2: Application Note: Virtex-4 Family o
Page 3 and 4: Data Plane DescriptionRData PlaneDe
Page 5 and 6: Data Plane DescriptionRThe MGT cloc
Page 7 and 8: Pattern GeneratorRrepresent a Fibon
Page 9 and 10: Pattern GeneratorRTable 3: Supporte
Page 11 and 12: Pattern GeneratorRTable 5: User Pat
Page 13 and 14: Pattern CheckerRresetrx_clocken_8b1
Page 15 and 16: Single-Channel XBERT ModuleRSingle-
Page 17: Multi-Channel XBERT ModuleRRESETSYS
Page 21 and 22: Multi-Channel XBERT ModuleRTable 9:
Page 23 and 24: Multi-Channel XBERT ModuleRTable 10
Page 25 and 26: Multi-Channel XBERT ModuleRTable 10
Page 27 and 28: Control Plane DescriptionRDCM_MODUL
Page 29 and 30: Software DescriptionRTable 12: Data
Page 31 and 32: Software DescriptionRTable 13: Conf
Page 33 and 34: Software DescriptionRSystem Reset o
Page 35 and 36: Design ConfigurationRThe software i
Page 37 and 38: Design ConfigurationRTable 15: Hard
Page 39 and 40: Reference DesignRReferenceDesignThe
Page 41 and 42: Reference DesignRSet EDK and Xilinx
Page 43: Revision HistoryR6. Xilinx, Inc., U

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