Volume 3: General-Purpose and System Instructions - Stanford ...
Volume 3: General-Purpose and System Instructions - Stanford ... Volume 3: General-Purpose and System Instructions - Stanford ...
AMD64 Technology 24594 Rev. 3.10 February 2005Mnemonic Opcode DescriptionADD reg16, reg/mem16 03 /r Add reg/mem16 to reg16.ADD reg32, reg/mem32 03 /r Add reg/mem32 to reg32.ADD reg64, reg/mem64 03 /r Add reg/mem64 to reg64.Related InstructionsADC, SBB, SUBrFLAGS AffectedID VIP VIF AC VM RF NT IOPL OF DF IF TF SF ZF AF PF CFExceptionsM M M M M M21 20 19 18 17 16 14 13–12 11 10 9 8 7 6 4 2 0Note: Bits 31–22, 15, 5, 3, and 1 are reserved. A flag set to 1 or cleared to 0 is M (modified). Unaffected flags are blank. Undefinedflags are U.Exception RealVirtual8086 Protected Cause of ExceptionStack, #SS X X X A memory address exceeded the stack segment limit or was noncanonical.General protection,#GPX X XA memory address exceeded a data segment limit or was non-canonical.XThe destination operand was in a non-writable segment.X A null data segment was used to reference memory.Page fault, #PF X X A page fault resulted from the execution of the instruction.Alignment check, #AC X X An unaligned memory reference was performed while alignmentchecking was enabled.68 ADD
24594 Rev. 3.10 February 2005 AMD64 TechnologyANDLogical ANDPerforms a bitwise AND operation on the value in a register or memory location (firstoperand) and an immediate value or the value in a register or memory location(second operand), and stores the result in the first operand location. The instructioncannot AND two memory operands.The instruction sets each bit of the result to 1 if the corresponding bit of bothoperands is set; otherwise, it clears the bit to 0. The following table shows the truthtable for the AND operation:X Y X AND Y0 0 00 1 01 0 01 1 1The forms of the AND instruction that write to memory support the LOCK prefix. Fordetails about the LOCK prefix, see “Lock Prefix” on page 10.Mnemonic Opcode DescriptionAND AL, imm8AND AX, imm16AND EAX, imm32AND RAX, imm3224 ib25 iw25 id25 idAND the contents of AL with an immediate 8-bit value and storethe result in AL.AND the contents of AX with an immediate 16-bit value and storethe result in AX.AND the contents of EAX with an immediate 32-bit value andstore the result in EAX.AND the contents of RAX with a sign-extended immediate 32-bitvalue and store the result in RAX.AND reg/mem8, imm8 80 /4 ib AND the contents of reg/mem8 with imm8.AND reg/mem16, imm16 81 /4 iw AND the contents of reg/mem16 with imm16.AND reg/mem32, imm32 81 /4 id AND the contents of reg/mem32 with imm32.AND reg/mem64, imm32 81 /4 id AND the contents of reg/mem64 with sign-extended imm32.AND 69
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AMD64 Technology 24594 Rev. 3.10 February 2005Mnemonic Opcode DescriptionADD reg16, reg/mem16 03 /r Add reg/mem16 to reg16.ADD reg32, reg/mem32 03 /r Add reg/mem32 to reg32.ADD reg64, reg/mem64 03 /r Add reg/mem64 to reg64.Related <strong>Instructions</strong>ADC, SBB, SUBrFLAGS AffectedID VIP VIF AC VM RF NT IOPL OF DF IF TF SF ZF AF PF CFExceptionsM M M M M M21 20 19 18 17 16 14 13–12 11 10 9 8 7 6 4 2 0Note: Bits 31–22, 15, 5, 3, <strong>and</strong> 1 are reserved. A flag set to 1 or cleared to 0 is M (modified). Unaffected flags are blank. Undefinedflags are U.Exception RealVirtual8086 Protected Cause of ExceptionStack, #SS X X X A memory address exceeded the stack segment limit or was noncanonical.<strong>General</strong> protection,#GPX X XA memory address exceeded a data segment limit or was non-canonical.XThe destination oper<strong>and</strong> was in a non-writable segment.X A null data segment was used to reference memory.Page fault, #PF X X A page fault resulted from the execution of the instruction.Alignment check, #AC X X An unaligned memory reference was performed while alignmentchecking was enabled.68 ADD
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