Volume 3: General-Purpose and System Instructions - Stanford ...
Volume 3: General-Purpose and System Instructions - Stanford ... Volume 3: General-Purpose and System Instructions - Stanford ...
AMD64 Technology 24594 Rev. 3.10 February 2005Mnemonic Opcode DescriptionADC reg/mem64, reg64 11 /r Add reg64 to reg/mem64 + CF.ADC reg8, reg/mem8 12 /r Add reg/mem8 to reg8 + CF.ADC reg16, reg/mem16 13 /r Add reg/mem16 to reg16 + CF.ADC reg32, reg/mem32 13 /r Add reg/mem32 to reg32 + CF.ADC reg64, reg/mem64 13 /r Add reg/mem64 to reg64 + CF.Related InstructionsADD, SBB, SUBrFLAGS AffectedID VIP VIF AC VM RF NT IOPL OF DF IF TF SF ZF AF PF CFExceptionsM M M M M M21 20 19 18 17 16 14 13–12 11 10 9 8 7 6 4 2 0Note: Bits 31–22, 15, 5, 3, and 1 are reserved. A flag set to 1 or cleared to 0 is M (modified). Unaffected flags are blank. Undefinedflags are U.Exception RealVirtual8086 Protected Cause of ExceptionStack, #SS X X X A memory address exceeded the stack segment limit or was noncanonical.General protection,#GPX X XA memory address exceeded a data segment limit or was non-canonical.XThe destination operand was in a non-writable segment.X A null data segment was used to reference memory.Page fault, #PF X X A page fault resulted from the execution of the instruction.Alignment check, #AC X X An unaligned memory reference was performed while alignmentchecking was enabled.66 ADC
24594 Rev. 3.10 February 2005 AMD64 TechnologyADDSigned or Unsigned AddAdds the value in a register or memory location (first operand) and an immediatevalue or the value in a register a memory location (second operand), and stores theresult in the first operand location. The instruction cannot add two memory operands.The instruction sign-extends an immediate value to the length of the destinationregister or memory operand.This instruction evaluates the result for both signed and unsigned data types and setsthe OF and CF flags to indicate a carry in a signed or unsigned result, respectively. Itsets the SF flag to indicate the sign of a signed result.The forms of the ADD instruction that write to memory support the LOCK prefix. Fordetails about the LOCK prefix, see “Lock Prefix” on page 10.Mnemonic Opcode DescriptionADD AL, imm8 04 ib Add imm8 to AL.ADD AX, imm16 05 iw Add imm16 to AX.ADD EAX, imm32 05 id Add imm32 to EAX.ADD RAX, imm32 05 id Add sign-extended imm32 to RAX.ADD reg/mem8, imm8 80 /0 ib Add imm8 to reg/mem8.ADD reg/mem16, imm16 81 /0 iw Add imm16 to reg/mem16ADD reg/mem32, imm32 81 /0 id Add imm32 to reg/mem32.ADD reg/mem64, imm32 81 /0 id Add sign-extended imm32 to reg/mem64.ADD reg/mem16, imm8 83 /0 ib Add sign-extended imm8 to reg/mem16ADD reg/mem32, imm8 83 /0 ib Add sign-extended imm8 to reg/mem32.ADD reg/mem64, imm8 83 /0 ib Add sign-extended imm8 to reg/mem64.ADD reg/mem8, reg8 00 /r Add reg8 to reg/mem8.ADD reg/mem16, reg16 01 /r Add reg16 to reg/mem16.ADD reg/mem32, reg32 01 /r Add reg32 to reg/mem32.ADD reg/mem64, reg64 01 /r Add reg64 to reg/mem64.ADD reg8, reg/mem8 02 /r Add reg/mem8 to reg8.ADD 67
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24594 Rev. 3.10 February 2005 AMD64 TechnologyADDSigned or Unsigned AddAdds the value in a register or memory location (first oper<strong>and</strong>) <strong>and</strong> an immediatevalue or the value in a register a memory location (second oper<strong>and</strong>), <strong>and</strong> stores theresult in the first oper<strong>and</strong> location. The instruction cannot add two memory oper<strong>and</strong>s.The instruction sign-extends an immediate value to the length of the destinationregister or memory oper<strong>and</strong>.This instruction evaluates the result for both signed <strong>and</strong> unsigned data types <strong>and</strong> setsthe OF <strong>and</strong> CF flags to indicate a carry in a signed or unsigned result, respectively. Itsets the SF flag to indicate the sign of a signed result.The forms of the ADD instruction that write to memory support the LOCK prefix. Fordetails about the LOCK prefix, see “Lock Prefix” on page 10.Mnemonic Opcode DescriptionADD AL, imm8 04 ib Add imm8 to AL.ADD AX, imm16 05 iw Add imm16 to AX.ADD EAX, imm32 05 id Add imm32 to EAX.ADD RAX, imm32 05 id Add sign-extended imm32 to RAX.ADD reg/mem8, imm8 80 /0 ib Add imm8 to reg/mem8.ADD reg/mem16, imm16 81 /0 iw Add imm16 to reg/mem16ADD reg/mem32, imm32 81 /0 id Add imm32 to reg/mem32.ADD reg/mem64, imm32 81 /0 id Add sign-extended imm32 to reg/mem64.ADD reg/mem16, imm8 83 /0 ib Add sign-extended imm8 to reg/mem16ADD reg/mem32, imm8 83 /0 ib Add sign-extended imm8 to reg/mem32.ADD reg/mem64, imm8 83 /0 ib Add sign-extended imm8 to reg/mem64.ADD reg/mem8, reg8 00 /r Add reg8 to reg/mem8.ADD reg/mem16, reg16 01 /r Add reg16 to reg/mem16.ADD reg/mem32, reg32 01 /r Add reg32 to reg/mem32.ADD reg/mem64, reg64 01 /r Add reg64 to reg/mem64.ADD reg8, reg/mem8 02 /r Add reg/mem8 to reg8.ADD 67
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