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Volume 3: General-Purpose and System Instructions - Stanford ...

Volume 3: General-Purpose and System Instructions - Stanford ...

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AMD64 Technology 24594 Rev. 3.10 February 2005AADASCII Adjust Before DivisionConverts two unpacked BCD digits in the AL (least significant) <strong>and</strong> AH (mostsignificant) registers to a single binary value in the AL register using the followingformula:AL = ((10d * AH) + (AL))After the conversion, AH is cleared to 00h.In most modern assemblers, the AAD instruction adjusts from base-10 values.However, by coding the instruction directly in binary, it can adjust from any basespecified by the immediate byte value (ib) suffixed onto the D5h opcode. For example,code D508h for octal, D50Ah for decimal, <strong>and</strong> D50Ch for duodecimal (base 12).Using this instruction in 64-bit mode generates an invalid-opcode exception.Mnemonic Opcode DescriptionAAD(None)Related <strong>Instructions</strong>AAA, AAM, AASrFLAGS AffectedD5 0AD5 ibAdjust two BCD digits in AL <strong>and</strong> AH.(Invalid in 64-bit mode.)Adjust two BCD digits to the immediate byte base.(Invalid in 64-bit mode.)ID VIP VIF AC VM RF NT IOPL OF DF IF TF SF ZF AF PF CFExceptionsU M M U M U21 20 19 18 17 16 14 13–12 11 10 9 8 7 6 4 2 0Note: Bits 31–22, 15, 5, 3, <strong>and</strong> 1 are reserved. A flag set to 1 or cleared to 0 is M (modified). Unaffected flags are blank. Undefinedflags are U.VirtualException Real 8086 Protected Cause of ExceptionInvalid opcode, #UD X This instruction was executed in 64-bit mode.62 AAD

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