Volume 3: General-Purpose and System Instructions - Stanford ...
Volume 3: General-Purpose and System Instructions - Stanford ... Volume 3: General-Purpose and System Instructions - Stanford ...
AMD64 Technology 24594 Rev. 3.10 February 2005usage:temp_value = READ_BIT_ARRAY ([mem], bit_number)definition:temp_BYTE = READ_MEM.b [mem + (bit_number SHR 3)]// read the byte containing the bittemp_BIT = temp_BYTE SHR (bit_number & 7)// shift the requested bit position into bit 0return (temp_BIT & 0x01) // return ’0’ or ’1’58 Chapter 2: Instruction Overview
24594 Rev. 3.10 February 2005 AMD64 Technology3 General-Purpose Instruction ReferenceThis chapter describes the function, mnemonic syntax, opcodes,affected flags, and possible exceptions generated by thegeneral-purpose instructions. General-purpose instructions areused in basic software execution. Most of these instructionsload, store, or operate on data located in the general-purposeregisters (GPRs), in memory, or in both. The remaininginstructions are used to alter the sequential flow of the programby branching to other locations within the program, or toentirely different programs. With the exception of the MOVD,MOVMSKPD and MOVMSKPS instructions, which operate onMMX/XMM registers, the instructions within the category ofgeneral-purpose instructions do not operate on any otherregister set.Most general-purpose instructions are supported in allhardware implementations of the AMD64 architecture. Thefollowing general-purpose instructions are implemented only iftheir associated CPUID function bit is set:• CMPXCHG8B, indicated by bit 8 of CPUID standardfunction 1 and extended function 8000_0001h.• CMPXCHG16B, indicated by ECX bit 13 of CPUID standardfunction 1.• CMOVcc (conditional moves), indicated by bit 15 of CPUIDstandard function 1 and extended function 8000_0001h.• CLFLUSH, indicated by bit 19 of CPUID standard function1.• PREFETCH, indicated by bit 31 of CPUID extendedfunction 8000_0001h.• MOVD, indicated by bits 25 (MMX) and 26 (XMM) ofCPUID standard function 1.• MOVNTI, indicated by bit 26 of CPUID standard function 1.• SFENCE, indicated by bit 25 of CPUID standard function 1.• MFENCE, LFENCE, indicated by bit 26 of CPUID standardfunction 1.• Long Mode instructions, indicated by bit 29 of CPUIDextended function 8000_0001h.The general-purpose instructions can be used in legacy mode or64-bit long mode. Compilation of general-purpose programs for59
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24594 Rev. 3.10 February 2005 AMD64 Technology3 <strong>General</strong>-<strong>Purpose</strong> Instruction ReferenceThis chapter describes the function, mnemonic syntax, opcodes,affected flags, <strong>and</strong> possible exceptions generated by thegeneral-purpose instructions. <strong>General</strong>-purpose instructions areused in basic software execution. Most of these instructionsload, store, or operate on data located in the general-purposeregisters (GPRs), in memory, or in both. The remaininginstructions are used to alter the sequential flow of the programby branching to other locations within the program, or toentirely different programs. With the exception of the MOVD,MOVMSKPD <strong>and</strong> MOVMSKPS instructions, which operate onMMX/XMM registers, the instructions within the category ofgeneral-purpose instructions do not operate on any otherregister set.Most general-purpose instructions are supported in allhardware implementations of the AMD64 architecture. Thefollowing general-purpose instructions are implemented only iftheir associated CPUID function bit is set:• CMPXCHG8B, indicated by bit 8 of CPUID st<strong>and</strong>ardfunction 1 <strong>and</strong> extended function 8000_0001h.• CMPXCHG16B, indicated by ECX bit 13 of CPUID st<strong>and</strong>ardfunction 1.• CMOVcc (conditional moves), indicated by bit 15 of CPUIDst<strong>and</strong>ard function 1 <strong>and</strong> extended function 8000_0001h.• CLFLUSH, indicated by bit 19 of CPUID st<strong>and</strong>ard function1.• PREFETCH, indicated by bit 31 of CPUID extendedfunction 8000_0001h.• MOVD, indicated by bits 25 (MMX) <strong>and</strong> 26 (XMM) ofCPUID st<strong>and</strong>ard function 1.• MOVNTI, indicated by bit 26 of CPUID st<strong>and</strong>ard function 1.• SFENCE, indicated by bit 25 of CPUID st<strong>and</strong>ard function 1.• MFENCE, LFENCE, indicated by bit 26 of CPUID st<strong>and</strong>ardfunction 1.• Long Mode instructions, indicated by bit 29 of CPUIDextended function 8000_0001h.The general-purpose instructions can be used in legacy mode or64-bit long mode. Compilation of general-purpose programs for59
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