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AMD64 Technology 24594 Rev. 3.10 February 2005Table 2-1.Interrupt-Vector Source and CauseVector Interrupt (Exception) Mnemonic Source Cause0 Divide-By-Zero-Error #DE Software DIV, IDIV, AAM instructions1 Debug #DB Internal Instruction accesses and data accesses2 Non-Maskable-Interrupt #NMI External External NMI signal3 Breakpoint #BP Software INT3 instruction4 Overflow #OF Software INTO instruction5 Bound-Range #BR Software BOUND instruction6 Invalid-Opcode #UD Internal Invalid instructions7 Device-Not-Available #NM Internal x87 instructions8 Double-Fault #DF Internal Interrupt during an interrupt9 Coprocessor-Segment-Overrun — External Unsupported (reserved)10 Invalid-TSS #TS Internal Task-state segment access and task switch11 Segment-Not-Present #NP Internal Segment access through a descriptor12 Stack #SS Internal SS register loads and stack references13 General-Protection #GP Internal Memory accesses and protection checks14 Page-Fault #PF Internal Memory accesses when paging enabled15 Reserved —16 Floating-Point Exception-Pending #MF Softwarex87 floating-point and 64-bit mediafloating-point instructions17 Alignment-Check #AC Internal Memory accesses18 Machine-Check #MCInternalExternalModel specific19 SIMD Floating-Point #XF Internal 128-bit media floating-point instructions20—31 Reserved (Internal and External) —0—255 External Interrupts (Maskable) #INTR External External interrupt signal0—255 Software Interrupts — Software INTn instruction42 Chapter 2: Instruction Overview
24594 Rev. 3.10 February 2005 AMD64 Technology2.5 Notation2.5.1 MnemonicSyntaxEach instruction has a syntax that includes the mnemonic andany operands that the instruction can take. Figure 2-14 showsan example of a syntax in which the instruction takes twooperands. In most instructions that take two operands, the first(left-most) operand is both a source operand (the first sourceoperand) and the destination operand. The second (right-most)operand serves only as a source, not a destination.ADDPD xmm1, xmm2/mem128MnemonicFirst Source Operandand Destination OperandSecond Source Operand513-322.epsFigure 2-14.Syntax for Typical Two-Operand InstructionThe following notation is used to denote the size and type ofsource and destination operands:• cReg—Control register.• dReg—Debug register.• imm8—Byte (8-bit) immediate.• imm16—Word (16-bit) immediate.• imm16/32—Word (16-bit) or doubleword (32-bit) immediate.• imm32—Doubleword (32-bit) immediate.• imm32/64—Doubleword (32-bit) or quadword (64-bit)immediate.• imm64—Quadword (64-bit) immediate.• mem—An operand of unspecified size in memory.• mem8—Byte (8-bit) operand in memory.• mem16—Word (16-bit) operand in memory.• mem16/32—Word (16-bit) or doubleword (32-bit) operand inmemory.• mem32—Doubleword (32-bit) operand in memory.Chapter 2: Instruction Overview 43
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