Volume 3: General-Purpose and System Instructions - Stanford ...
Volume 3: General-Purpose and System Instructions - Stanford ... Volume 3: General-Purpose and System Instructions - Stanford ...
AMD64 Technology 24594 Rev. 3.10 February 20052.3 Summary of Registers and Data TypesThis section summarizes the registers available to softwareusing the five instruction subsets described in “InstructionSubsets” on page 27. For details on the organization and use ofthese registers, see their respective chapters in volumes 1 and 2.2.3.1 General-PurposeInstructionsRegisters. The size and number of general-purpose registers(GPRs) depends on the operating mode, as do the size of theflags and instruction-pointer registers. Figure 2-2 shows theregisters available in legacy and compatibility modes.registerencodinghigh8-bitlow8-bit16-bit32-bit0AH (4)ALAXEAX3BH (7)BLBXEBX1CH (5)CLCXECX2DH (6)DLDXEDX6SISIESI7DIDIEDI5BPBPEBP4SPSPESP31 16 15 0FLAGSIP31 0FLAGSIPEFLAGSEIP513-311.epsFigure 2-2.General Registers in Legacy and Compatibility ModesFigure 2-3 on page 31 shows the registers accessible in 64-bitmode. Compared with legacy mode, registers become 64 bitswide, eight new data registers (R8–R15) are added and the lowbyte of all 16 GPRs is available for byte operations, and the fourhigh-byte registers of legacy mode (AH, BH, CH, and DH) arenot available if the REX prefix is used. The high 32 bits of30 Chapter 2: Instruction Overview
24594 Rev. 3.10 February 2005 AMD64 Technologydoubleword operands are zero-extended to 64 bits, but the highbits of word and byte operands are not modified by operationsin 64-bit mode. The RFLAGS register is 64 bits wide, but thehigh 32 bits are reserved. They can be written with anything butthey read as zeros (RAZ).not modified for 8-bit operandsnot modified for 16-bit operandsregisterencodingzero-extendedfor 32-bit operandslow8-bit16-bit 32-bit 64-bit0AH*ALAXEAXRAX3BH*BLBXEBXRBX1CH*CLCXECXRCX2DH*DLDXEDXRDX6SIL**SIESIRSI7DIL**DIEDIRDI5BPL**BPEBPRBP4SPL**SPESPRSP8R8BR8WR8DR89R9BR9WR9DR910R10BR10WR10DR1011R11BR11WR11DR1112R12BR12WR12DR1213R13BR13WR13DR1314R14BR14WR14DR1415R15BR15WR15DR1563 32 31 16 15 8 7 0Figure 2-3.063 32 31 0General Registers in 64-Bit ModeRFLAGSRIP513-309.eps* Not addressable whena REX prefix is used.** Only addressable whena REX prefix is used.Chapter 2: Instruction Overview 31
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AMD64 Technology 24594 Rev. 3.10 February 20052.3 Summary of Registers <strong>and</strong> Data TypesThis section summarizes the registers available to softwareusing the five instruction subsets described in “InstructionSubsets” on page 27. For details on the organization <strong>and</strong> use ofthese registers, see their respective chapters in volumes 1 <strong>and</strong> 2.2.3.1 <strong>General</strong>-<strong>Purpose</strong><strong>Instructions</strong>Registers. The size <strong>and</strong> number of general-purpose registers(GPRs) depends on the operating mode, as do the size of theflags <strong>and</strong> instruction-pointer registers. Figure 2-2 shows theregisters available in legacy <strong>and</strong> compatibility modes.registerencodinghigh8-bitlow8-bit16-bit32-bit0AH (4)ALAXEAX3BH (7)BLBXEBX1CH (5)CLCXECX2DH (6)DLDXEDX6SISIESI7DIDIEDI5BPBPEBP4SPSPESP31 16 15 0FLAGSIP31 0FLAGSIPEFLAGSEIP513-311.epsFigure 2-2.<strong>General</strong> Registers in Legacy <strong>and</strong> Compatibility ModesFigure 2-3 on page 31 shows the registers accessible in 64-bitmode. Compared with legacy mode, registers become 64 bitswide, eight new data registers (R8–R15) are added <strong>and</strong> the lowbyte of all 16 GPRs is available for byte operations, <strong>and</strong> the fourhigh-byte registers of legacy mode (AH, BH, CH, <strong>and</strong> DH) arenot available if the REX prefix is used. The high 32 bits of30 Chapter 2: Instruction Overview
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