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AMD64 Technology 24594 Rev. 3.10 February 2005492 Appendix D: Instruction Subsets and CPUID Feature Sets
24594 Rev. 3.10 February 2005 AMD64 TechnologyAppendix EInstruction Effects on RFLAGSThe flags in the RFLAGS register are described in “FlagsRegister” in Volume 1 and “RFLAGS Register” in Volume 2.Table E-1 summarizes the effect that instructions have on theseflags. The table includes all instructions that affect the flags.Instructions not shown have no effect on RFLAGS.The following codes are used within the table:• 0—The flag is always cleared to 0.• 1—The flag is always set to 1.• AH—The flag is loaded with value from AH register.• Mod—The flag is modified, depending on the results of theinstruction.• Pop—The flag is loaded with value popped off of the stack.• Tst—The flag is tested.• U—The effect on the flag is undefined.• Gray shaded cells indicate that the flag is not affected by theinstruction.Table E-1.Instruction Effects on RFLAGSInstructionMnemonicID21VIP20VIF19AC18VM17RFLAGS Mnemonic and Bit NumberRF16NT14IOPL13-12OF11DF10IF9TF8SF7ZF6AF4PF2CF0AAAAASU U UTstModUModAADAAMUMod Mod U Mod UADC Mod Mod Mod Mod ModTstModADD Mod Mod Mod Mod Mod ModAND 0 Mod Mod U Mod 0ARPLBSFBSRModU U Mod U U UAppendix E: Instruction Effects on RFLAGS 493
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