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Volume 3: General-Purpose and System Instructions - Stanford ...

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24594 Rev. 3.10 February 2005 AMD64 TechnologyTable D-1.Instruction Subsets <strong>and</strong> CPUID Feature Sets (continued)UNPCKLPDUNPCKLPSUnpack Low Double-Precision Floating-PointUnpack Low Single-Precision Floating-Point33VERR Verify Segment for Reads 3 BasicVERWWAITWBINVDWRMSRVerify Segment forWritesWait for x87 Floating-Point ExceptionsWriteback <strong>and</strong> InvalidateCachesWrite to Model-SpecificRegisterXADD Exchange <strong>and</strong> Add 3 BasicXCHG Exchange 3 BasicXLAT Translate Table Index 3 BasicXLATBTranslate Table Index(No Oper<strong>and</strong>s)33003BasicXOR Exclusive OR 3 BasicXORPDXORPSInstructionMnemonic Description CPLLogical Bitwise ExclusiveOR Packed Double-Precision Floating-PointLogical Bitwise ExclusiveOR Packed Single-Precision Floating-Point33<strong>General</strong>-<strong>Purpose</strong>Instruction Subset<strong>and</strong> CPUID Feature Set(s) 1128-BitMediaSSE2SSESSE2SSE64-BitMedia1. Columns indicate the instruction subsets. Entries indicate the CPUID feature set(s) to which the instruction belongs.2. Mnemonic is used for two different instructions. Assemblers can distinguish them by the number <strong>and</strong> type of oper<strong>and</strong>s.x87X87<strong>System</strong>BasicBasicRDMSR,WRMSRAppendix D: Instruction Subsets <strong>and</strong> CPUID Feature Sets 491

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