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Volume 3: General-Purpose and System Instructions - Stanford ...

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AMD64 Technology 24594 Rev. 3.10 February 2005Table D-1.Instruction Subsets <strong>and</strong> CPUID Feature Sets (continued)SUBPSSUBSDSUBSSSWAPGSSubtract Packed Single-Precision Floating-PointSubtract Scalar Double-Precision Floating-PointSubtract Scalar Single-Precision Floating-PointSwap GS Register withKernelGSbase MSRSYSCALL Fast <strong>System</strong> Call 3SYSENTER <strong>System</strong> Call 3SYSEXIT <strong>System</strong> Return 0SYSRET Fast <strong>System</strong> Return 0TEST Test Bits 3 BasicUCOMISDUCOMISSUnordered CompareScalar Double-PrecisionFloating-PointUnordered CompareScalar Single-PrecisionFloating-Point333033SSESSE2SSESSE2SSELong ModeSYSCALL,SYSRETSYSENTER,SYSEXITSYSENTER,SYSEXITSYSCALL,SYSRETUD2 Undefined Operation 3 BasicUNPCKHPDUNPCKHPSInstructionMnemonic Description CPLUnpack High Double-Precision Floating-PointUnpack High Single-Precision Floating-Point33<strong>General</strong>-<strong>Purpose</strong>Instruction Subset<strong>and</strong> CPUID Feature Set(s) 1128-BitMediaSSE2SSE64-BitMedia1. Columns indicate the instruction subsets. Entries indicate the CPUID feature set(s) to which the instruction belongs.2. Mnemonic is used for two different instructions. Assemblers can distinguish them by the number <strong>and</strong> type of oper<strong>and</strong>s.x87<strong>System</strong>490 Appendix D: Instruction Subsets <strong>and</strong> CPUID Feature Sets

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