Volume 3: General-Purpose and System Instructions - Stanford ...
Volume 3: General-Purpose and System Instructions - Stanford ... Volume 3: General-Purpose and System Instructions - Stanford ...
AMD64 Technology 24594 Rev. 3.10 February 2005Table D-1.Instruction Subsets and CPUID Feature Sets (continued)SCAS Scan String 3 BasicSCASB Scan String as Bytes 3 BasicSCASDSCASQScan String asDoublewordScan String asQuadword33BasicLong ModeSCASW Scan String as Words 3 BasicSETcc Set Byte if Condition 3 BasicSFENCE Store Fence 3SGDTStore Global DescriptorTable Register3SSE, MMXExtensionsSHL Shift Left 3 BasicSHLD Shift Left Double 3 BasicSHR Shift Right 3 BasicSHRD Shift Right Double 3 BasicSHUFPDSHUFPSSIDTSLDTSMSWInstructionMnemonic Description CPLShuffle Packed Double-Precision Floating-PointShuffle Packed Single-Precision Floating-PointStore InterruptDescriptor Table RegisterStore Local DescriptorTable RegisterStore Machine StatusWord33333General-PurposeInstruction Subsetand CPUID Feature Set(s) 1128-BitMediaSSE2SSE64-BitMediax87SystemBasicBasicBasicBasic1. Columns indicate the instruction subsets. Entries indicate the CPUID feature set(s) to which the instruction belongs.2. Mnemonic is used for two different instructions. Assemblers can distinguish them by the number and type of operands.488 Appendix D: Instruction Subsets and CPUID Feature Sets
24594 Rev. 3.10 February 2005 AMD64 TechnologyTable D-1.Instruction Subsets and CPUID Feature Sets (continued)SQRTPDSQRTPSSQRTSDSQRTSSSquare Root PackedDouble-PrecisionFloating-PointSquare Root PackedSingle-PrecisionFloating-PointSquare Root ScalarDouble-PrecisionFloating-PointSquare Root ScalarSingle-PrecisionFloating-PointSTC Set Carry Flag 3 BasicSTD Set Direction Flag 3 Basic3333STI Set Interrupt Flag 3 BasicSTMXCSRStore MXCSRControl/Status RegisterSTOS Store String 3 BasicSTOSB Store String Bytes 3 BasicSTOSDStore StringDoublewords33BasicSTOSQ Store String Quadwords 3 Long ModeSTOSW Store String Words 3 BasicSTR Store Task Register 3 BasicSUB Subtract 3 BasicSUBPDInstructionMnemonic Description CPLSubtract Packed Double-Precision Floating-Point3General-PurposeInstruction Subsetand CPUID Feature Set(s) 1128-BitMediaSSE2SSESSE2SSESSESSE264-BitMedia1. Columns indicate the instruction subsets. Entries indicate the CPUID feature set(s) to which the instruction belongs.2. Mnemonic is used for two different instructions. Assemblers can distinguish them by the number and type of operands.x87SystemAppendix D: Instruction Subsets and CPUID Feature Sets 489
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AMD64 Technology 24594 Rev. 3.10 February 2005Table D-1.Instruction Subsets <strong>and</strong> CPUID Feature Sets (continued)SCAS Scan String 3 BasicSCASB Scan String as Bytes 3 BasicSCASDSCASQScan String asDoublewordScan String asQuadword33BasicLong ModeSCASW Scan String as Words 3 BasicSETcc Set Byte if Condition 3 BasicSFENCE Store Fence 3SGDTStore Global DescriptorTable Register3SSE, MMXExtensionsSHL Shift Left 3 BasicSHLD Shift Left Double 3 BasicSHR Shift Right 3 BasicSHRD Shift Right Double 3 BasicSHUFPDSHUFPSSIDTSLDTSMSWInstructionMnemonic Description CPLShuffle Packed Double-Precision Floating-PointShuffle Packed Single-Precision Floating-PointStore InterruptDescriptor Table RegisterStore Local DescriptorTable RegisterStore Machine StatusWord33333<strong>General</strong>-<strong>Purpose</strong>Instruction Subset<strong>and</strong> CPUID Feature Set(s) 1128-BitMediaSSE2SSE64-BitMediax87<strong>System</strong>BasicBasicBasicBasic1. Columns indicate the instruction subsets. Entries indicate the CPUID feature set(s) to which the instruction belongs.2. Mnemonic is used for two different instructions. Assemblers can distinguish them by the number <strong>and</strong> type of oper<strong>and</strong>s.488 Appendix D: Instruction Subsets <strong>and</strong> CPUID Feature Sets
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