Volume 3: General-Purpose and System Instructions - Stanford ...
Volume 3: General-Purpose and System Instructions - Stanford ... Volume 3: General-Purpose and System Instructions - Stanford ...
AMD64 Technology 24594 Rev. 3.10 February 2005Table D-1.Instruction Subsets and CPUID Feature Sets (continued)PUNPCKHWDPUNPCKLBWPUNPCKLDQPUNPCKLQDQPUNPCKLWDUnpack and InterleaveHigh WordsUnpack and InterleaveLow BytesUnpack and InterleaveLow DoublewordsUnpack and InterleaveLow QuadwordsUnpack and InterleaveLow WordsPUSH Push onto Stack 3 BasicPUSHAPUSHADPUSHFPUSHFDPUSHFQPXORRCLRCPPSInstructionMnemonic Description CPLPush All GPR Words ontoStackPush All GPRDoublewords onto StackPush EFLAGS Word ontoStackPush EFLAGSDoubleword onto StackPush RFLAGS Quadwordonto StackPacked Logical BitwiseExclusive ORRotate Through CarryLeftReciprocal PackedSingle-PrecisionFloating-Point3333333333333General-PurposeBasicBasicBasicBasicLong ModeBasicInstruction Subsetand CPUID Feature Set(s) 1128-BitMediaSSE2SSE2SSE2SSE2SSE2SSE2SSE64-BitMediaMMXMMXMMX3DNow!MMXx87System1. Columns indicate the instruction subsets. Entries indicate the CPUID feature set(s) to which the instruction belongs.2. Mnemonic is used for two different instructions. Assemblers can distinguish them by the number and type of operands.486 Appendix D: Instruction Subsets and CPUID Feature Sets
24594 Rev. 3.10 February 2005 AMD64 TechnologyTable D-1.Instruction Subsets and CPUID Feature Sets (continued)RCPSSRCRRDMSRRDPMCRDTSCRDTSCPReciprocal Scalar Single-Precision Floating-PointRotate Through CarryRightRead Model-SpecificRegisterRead Performance-Monitoring CounterRead Time-StampCounterRead Time-StampCounter and ProcessorID33033BasicRET Return from Call 3 BasicROL Rotate Left 3 BasicROR Rotate Right 3 BasicRSMRSQRTPSRSQRTSSInstructionMnemonic Description CPLResume from SystemManagement ModeReciprocal Square RootPacked Single-PrecisionFloating-PointReciprocal Square RootScalar Single-PrecisionFloating-Point3333General-PurposeSAHF Store AH into Flags 3 BasicSAL Shift Arithmetic Left 3 BasicSAR Shift Arithmetic Right 3 BasicSBB Subtract with Borrow 3 BasicInstruction Subsetand CPUID Feature Set(s) 1128-BitMediaSSESSESSE64-BitMediax87SystemRDMSR,WRMSRBasicTSCRDTSCPBasic1. Columns indicate the instruction subsets. Entries indicate the CPUID feature set(s) to which the instruction belongs.2. Mnemonic is used for two different instructions. Assemblers can distinguish them by the number and type of operands.Appendix D: Instruction Subsets and CPUID Feature Sets 487
- Page 466 and 467: AMD64 Technology 24594 Rev. 3.10 Fe
- Page 468 and 469: AMD64 Technology 24594 Rev. 3.10 Fe
- Page 470 and 471: AMD64 Technology 24594 Rev. 3.10 Fe
- Page 472 and 473: AMD64 Technology 24594 Rev. 3.10 Fe
- Page 474 and 475: AMD64 Technology 24594 Rev. 3.10 Fe
- Page 476 and 477: AMD64 Technology 24594 Rev. 3.10 Fe
- Page 478 and 479: AMD64 Technology 24594 Rev. 3.10 Fe
- Page 480 and 481: AMD64 Technology 24594 Rev. 3.10 Fe
- Page 482 and 483: AMD64 Technology 24594 Rev. 3.10 Fe
- Page 484 and 485: AMD64 Technology 24594 Rev. 3.10 Fe
- Page 486 and 487: AMD64 Technology 24594 Rev. 3.10 Fe
- Page 488 and 489: AMD64 Technology 24594 Rev. 3.10 Fe
- Page 490 and 491: AMD64 Technology 24594 Rev. 3.10 Fe
- Page 492 and 493: AMD64 Technology 24594 Rev. 3.10 Fe
- Page 494 and 495: AMD64 Technology 24594 Rev. 3.10 Fe
- Page 496 and 497: AMD64 Technology 24594 Rev. 3.10 Fe
- Page 498 and 499: AMD64 Technology 24594 Rev. 3.10 Fe
- Page 500 and 501: AMD64 Technology 24594 Rev. 3.10 Fe
- Page 502 and 503: AMD64 Technology 24594 Rev. 3.10 Fe
- Page 504 and 505: AMD64 Technology 24594 Rev. 3.10 Fe
- Page 506 and 507: AMD64 Technology 24594 Rev. 3.10 Fe
- Page 508 and 509: AMD64 Technology 24594 Rev. 3.10 Fe
- Page 510 and 511: AMD64 Technology 24594 Rev. 3.10 Fe
- Page 512 and 513: AMD64 Technology 24594 Rev. 3.10 Fe
- Page 514 and 515: AMD64 Technology 24594 Rev. 3.10 Fe
- Page 518 and 519: AMD64 Technology 24594 Rev. 3.10 Fe
- Page 520 and 521: AMD64 Technology 24594 Rev. 3.10 Fe
- Page 522 and 523: AMD64 Technology 24594 Rev. 3.10 Fe
- Page 524 and 525: AMD64 Technology 24594 Rev. 3.10 Fe
- Page 526 and 527: AMD64 Technology 24594 Rev. 3.10 Fe
- Page 528 and 529: AMD64 Technology 24594 Rev. 3.10 Fe
- Page 530 and 531: AMD64 Technology 24594 Rev. 3.10 Fe
- Page 532 and 533: AMD64 Technology 24594 Rev. 3.10 Fe
- Page 534: AMD64 Technology 24594 Rev. 3.10 Fe
AMD64 Technology 24594 Rev. 3.10 February 2005Table D-1.Instruction Subsets <strong>and</strong> CPUID Feature Sets (continued)PUNPCKHWDPUNPCKLBWPUNPCKLDQPUNPCKLQDQPUNPCKLWDUnpack <strong>and</strong> InterleaveHigh WordsUnpack <strong>and</strong> InterleaveLow BytesUnpack <strong>and</strong> InterleaveLow DoublewordsUnpack <strong>and</strong> InterleaveLow QuadwordsUnpack <strong>and</strong> InterleaveLow WordsPUSH Push onto Stack 3 BasicPUSHAPUSHADPUSHFPUSHFDPUSHFQPXORRCLRCPPSInstructionMnemonic Description CPLPush All GPR Words ontoStackPush All GPRDoublewords onto StackPush EFLAGS Word ontoStackPush EFLAGSDoubleword onto StackPush RFLAGS Quadwordonto StackPacked Logical BitwiseExclusive ORRotate Through CarryLeftReciprocal PackedSingle-PrecisionFloating-Point3333333333333<strong>General</strong>-<strong>Purpose</strong>BasicBasicBasicBasicLong ModeBasicInstruction Subset<strong>and</strong> CPUID Feature Set(s) 1128-BitMediaSSE2SSE2SSE2SSE2SSE2SSE2SSE64-BitMediaMMXMMXMMX3DNow!MMXx87<strong>System</strong>1. Columns indicate the instruction subsets. Entries indicate the CPUID feature set(s) to which the instruction belongs.2. Mnemonic is used for two different instructions. Assemblers can distinguish them by the number <strong>and</strong> type of oper<strong>and</strong>s.486 Appendix D: Instruction Subsets <strong>and</strong> CPUID Feature Sets
Change language