Volume 3: General-Purpose and System Instructions - Stanford ...

24594 Rev. 3.10 February 2005 AMD64 TechnologyTable D-1.Instruction Subsets and CPUID Feature Sets (continued)PSRLQPSRLWPacked Shift RightLogical QuadwordsPacked Shift RightLogical Words33SSE2SSE2MMXMMXPSUBB Packed Subtract Bytes 3 SSE2 MMXPSUBDPSUBQPSUBSBPSUBSWPSUBUSBPSUBUSWPacked SubtractDoublewordsPacked SubtractQuadwordPacked Subtract SignedWith Saturation BytesPacked Subtract Signedwith Saturation WordsPacked SubtractUnsigned and SaturateBytesPacked SubtractUnsigned and SaturateWords333333SSE2SSE2SSE2SSE2SSE2SSE2MMXSSE2MMXMMXMMXMMXPSUBW Packed Subtract Words 3 SSE2 MMXPSWAPDPUNPCKHBWPUNPCKHDQPUNPCKHQDQInstructionMnemonic Description CPLPacked SwapDoublewordUnpack and InterleaveHigh BytesUnpack and InterleaveHigh DoublewordsUnpack and InterleaveHigh Quadwords3333General-PurposeInstruction Subsetand CPUID Feature Set(s) 1128-BitMediaSSE2SSE2SSE264-BitMedia3DNow!ExtensionsMMXMMXx87System1. Columns indicate the instruction subsets. Entries indicate the CPUID feature set(s) to which the instruction belongs.2. Mnemonic is used for two different instructions. Assemblers can distinguish them by the number and type of operands.Appendix D: Instruction Subsets and CPUID Feature Sets 485