Volume 3: General-Purpose and System Instructions - Stanford ...

AMD64 Technology 24594 Rev. 3.10 February 2005Table D-1.Instruction Subsets and CPUID Feature Sets (continued)INSD Input String Doubleword 3 BasicINSW Input String Word 3 BasicINT Interrupt to Vector 3 BasicINT 3INTOInterrupt to DebugVectorInterrupt to OverflowVector3 Basic3 BasicINVD Invalidate Caches 0 BasicINVLPG Invalidate TLB Entry 0 BasicIRET Interrupt Return Word 3 BasicIRETDIRETQInterrupt ReturnDoublewordInterrupt ReturnQuadwordJcc Jump Condition 3 BasicJCXZ Jump if CX Zero 3 BasicJECXZ Jump if ECX Zero 3 BasicJMP Jump 3 BasicJRCXZ Jump if RCX Zero 3 BasicLAHFLoad Status Flags intoAH Register333BasicBasicLongModeLAR Load Access Rights Byte 3 BasicLDDQULDMXCSRInstructionMnemonic Description CPLLoad Unaligned DoubleQuadwordLoad MXCSRControl/Status Register33General-PurposeInstruction Subsetand CPUID Feature Set(s) 1128-BitMediaSSE3SSE64-BitMedia1. Columns indicate the instruction subsets. Entries indicate the CPUID feature set(s) to which the instruction belongs.2. Mnemonic is used for two different instructions. Assemblers can distinguish them by the number and type of operands.x87System472 Appendix D: Instruction Subsets and CPUID Feature Sets