Volume 3: General-Purpose and System Instructions - Stanford ...
Volume 3: General-Purpose and System Instructions - Stanford ... Volume 3: General-Purpose and System Instructions - Stanford ...
AMD64 Technology 24594 Rev. 3.10 February 2005Table D-1.Instruction Subsets and CPUID Feature Sets (continued)CWDEDAADASConvert Word toDoublewordDecimal Adjust afterAdditionDecimal Adjust afterSubtraction333BasicBasicBasicDEC Decrement by 1 3 BasicDIV Unsigned Divide 3 BasicDIVPDDIVPSDIVSDDIVSSEMMSENTERF2XM1FABSDivide Packed Double-Precision Floating-PointDivide Packed Single-Precision Floating-PointDivide Scalar Double-Precision Floating-PointDivide Scalar Single-Precision Floating-PointEnter/Exit MultimediaStateCreate Procedure StackFrameFloating-Point Compute2x–1Floating-Point AbsoluteValue33333333BasicSSE2SSESSE2SSEMMXFADD Floating-Point Add 3 X87FADDPInstructionMnemonic Description CPLFloating-Point Add andPop3General-PurposeInstruction Subsetand CPUID Feature Set(s) 1128-BitMedia64-BitMediax87MMXX87X87X87System1. Columns indicate the instruction subsets. Entries indicate the CPUID feature set(s) to which the instruction belongs.2. Mnemonic is used for two different instructions. Assemblers can distinguish them by the number and type of operands.464 Appendix D: Instruction Subsets and CPUID Feature Sets
24594 Rev. 3.10 February 2005 AMD64 TechnologyTable D-1.Instruction Subsets and CPUID Feature Sets (continued)InstructionInstruction Subsetand CPUID Feature Set(s) 1Mnemonic Description CPLGeneral-Purpose128-BitMedia64-BitMediax87SystemFBLDFloating-Point LoadBinary-Coded Decimal3X87FBSTPFloating-Point StoreBinary-Coded DecimalInteger and Pop3X87FCHSFloating-Point ChangeSign3X87FCLEXFloating-Point ClearFlags3X87FCMOVBFloating-PointConditional Move IfBelow3X87,CMOVccFCMOVBEFloating-PointConditional Move IfBelow or Equal3X87,CMOVccFCMOVEFloating-PointConditional Move IfEqual3X87,CMOVccFCMOVNBFloating-PointConditional Move If NotBelow3X87,CMOVccFCMOVNBEFloating-PointConditional Move If NotBelow or Equal3X87,CMOVccFCMOVNEFloating-PointConditional Move If NotEqual3X87,CMOVccFCMOVNUFloating-PointConditional Move If NotUnordered3X87,CMOVcc1. Columns indicate the instruction subsets. Entries indicate the CPUID feature set(s) to which the instruction belongs.2. Mnemonic is used for two different instructions. Assemblers can distinguish them by the number and type of operands.Appendix D: Instruction Subsets and CPUID Feature Sets 465
- Page 444 and 445: AMD64 Technology 24594 Rev. 3.10 Fe
- Page 446 and 447: AMD64 Technology 24594 Rev. 3.10 Fe
- Page 448 and 449: AMD64 Technology 24594 Rev. 3.10 Fe
- Page 450 and 451: AMD64 Technology 24594 Rev. 3.10 Fe
- Page 452 and 453: AMD64 Technology 24594 Rev. 3.10 Fe
- Page 454 and 455: AMD64 Technology 24594 Rev. 3.10 Fe
- Page 456 and 457: AMD64 Technology 24594 Rev. 3.10 Fe
- Page 458 and 459: AMD64 Technology 24594 Rev. 3.10 Fe
- Page 460 and 461: AMD64 Technology 24594 Rev. 3.10 Fe
- Page 462 and 463: AMD64 Technology 24594 Rev. 3.10 Fe
- Page 464 and 465: AMD64 Technology 24594 Rev. 3.10 Fe
- Page 466 and 467: AMD64 Technology 24594 Rev. 3.10 Fe
- Page 468 and 469: AMD64 Technology 24594 Rev. 3.10 Fe
- Page 470 and 471: AMD64 Technology 24594 Rev. 3.10 Fe
- Page 472 and 473: AMD64 Technology 24594 Rev. 3.10 Fe
- Page 474 and 475: AMD64 Technology 24594 Rev. 3.10 Fe
- Page 476 and 477: AMD64 Technology 24594 Rev. 3.10 Fe
- Page 478 and 479: AMD64 Technology 24594 Rev. 3.10 Fe
- Page 480 and 481: AMD64 Technology 24594 Rev. 3.10 Fe
- Page 482 and 483: AMD64 Technology 24594 Rev. 3.10 Fe
- Page 484 and 485: AMD64 Technology 24594 Rev. 3.10 Fe
- Page 486 and 487: AMD64 Technology 24594 Rev. 3.10 Fe
- Page 488 and 489: AMD64 Technology 24594 Rev. 3.10 Fe
- Page 490 and 491: AMD64 Technology 24594 Rev. 3.10 Fe
- Page 492 and 493: AMD64 Technology 24594 Rev. 3.10 Fe
- Page 496 and 497: AMD64 Technology 24594 Rev. 3.10 Fe
- Page 498 and 499: AMD64 Technology 24594 Rev. 3.10 Fe
- Page 500 and 501: AMD64 Technology 24594 Rev. 3.10 Fe
- Page 502 and 503: AMD64 Technology 24594 Rev. 3.10 Fe
- Page 504 and 505: AMD64 Technology 24594 Rev. 3.10 Fe
- Page 506 and 507: AMD64 Technology 24594 Rev. 3.10 Fe
- Page 508 and 509: AMD64 Technology 24594 Rev. 3.10 Fe
- Page 510 and 511: AMD64 Technology 24594 Rev. 3.10 Fe
- Page 512 and 513: AMD64 Technology 24594 Rev. 3.10 Fe
- Page 514 and 515: AMD64 Technology 24594 Rev. 3.10 Fe
- Page 516 and 517: AMD64 Technology 24594 Rev. 3.10 Fe
- Page 518 and 519: AMD64 Technology 24594 Rev. 3.10 Fe
- Page 520 and 521: AMD64 Technology 24594 Rev. 3.10 Fe
- Page 522 and 523: AMD64 Technology 24594 Rev. 3.10 Fe
- Page 524 and 525: AMD64 Technology 24594 Rev. 3.10 Fe
- Page 526 and 527: AMD64 Technology 24594 Rev. 3.10 Fe
- Page 528 and 529: AMD64 Technology 24594 Rev. 3.10 Fe
- Page 530 and 531: AMD64 Technology 24594 Rev. 3.10 Fe
- Page 532 and 533: AMD64 Technology 24594 Rev. 3.10 Fe
- Page 534: AMD64 Technology 24594 Rev. 3.10 Fe
24594 Rev. 3.10 February 2005 AMD64 TechnologyTable D-1.Instruction Subsets <strong>and</strong> CPUID Feature Sets (continued)InstructionInstruction Subset<strong>and</strong> CPUID Feature Set(s) 1Mnemonic Description CPL<strong>General</strong>-<strong>Purpose</strong>128-BitMedia64-BitMediax87<strong>System</strong>FBLDFloating-Point LoadBinary-Coded Decimal3X87FBSTPFloating-Point StoreBinary-Coded DecimalInteger <strong>and</strong> Pop3X87FCHSFloating-Point ChangeSign3X87FCLEXFloating-Point ClearFlags3X87FCMOVBFloating-PointConditional Move IfBelow3X87,CMOVccFCMOVBEFloating-PointConditional Move IfBelow or Equal3X87,CMOVccFCMOVEFloating-PointConditional Move IfEqual3X87,CMOVccFCMOVNBFloating-PointConditional Move If NotBelow3X87,CMOVccFCMOVNBEFloating-PointConditional Move If NotBelow or Equal3X87,CMOVccFCMOVNEFloating-PointConditional Move If NotEqual3X87,CMOVccFCMOVNUFloating-PointConditional Move If NotUnordered3X87,CMOVcc1. Columns indicate the instruction subsets. Entries indicate the CPUID feature set(s) to which the instruction belongs.2. Mnemonic is used for two different instructions. Assemblers can distinguish them by the number <strong>and</strong> type of oper<strong>and</strong>s.Appendix D: Instruction Subsets <strong>and</strong> CPUID Feature Sets 465