Volume 3: General-Purpose and System Instructions - Stanford ...
Volume 3: General-Purpose and System Instructions - Stanford ... Volume 3: General-Purpose and System Instructions - Stanford ...
AMD64 Technology 24594 Rev. 3.10 February 2005Table D-1.Instruction Subsets and CPUID Feature Sets (continued)CMPPSCompare Packed Single-Precision Floating-PointCMPS Compare Strings 3 BasicCMPSB Compare Strings by Byte 3 BasicCMPSDCMPSDCMPSQCMPSSCMPSWCompare Strings byDoublewordCompare Scalar Double-Precision Floating-PointCompare Strings byQuadwordCompare Scalar Single-Precision Floating-PointCompare Strings byWord333333Basic 2Long ModeBasicCMPXCHG Compare and Exchange 3 BasicCMPXCHG8BCMPXCHG16BCOMISDCOMISSCompare and ExchangeEight BytesCompare and ExchangeSixteen BytesCompare Ordered ScalarDouble-PrecisionFloating-PointCompare Ordered ScalarSingle-PrecisionFloating-Point333CMPXCHG8BCMPXCHG16BCPUID Processor Identification 3 BasicCQOInstructionMnemonic Description CPLConvert Quadword toDouble Quadword33General-PurposeLong ModeInstruction Subsetand CPUID Feature Set(s) 1128-BitMediaSSESSE2 2SSESSE2SSE64-BitMediax87System1. Columns indicate the instruction subsets. Entries indicate the CPUID feature set(s) to which the instruction belongs.2. Mnemonic is used for two different instructions. Assemblers can distinguish them by the number and type of operands.460 Appendix D: Instruction Subsets and CPUID Feature Sets
24594 Rev. 3.10 February 2005 AMD64 TechnologyTable D-1.Instruction Subsets and CPUID Feature Sets (continued)InstructionInstruction Subsetand CPUID Feature Set(s) 1Mnemonic Description CPLGeneral-Purpose128-BitMedia64-BitMediax87SystemCVTDQ2PDConvert PackedDoubleword Integers toPacked Double-PrecisionFloating-Point3SSE2CVTDQ2PSConvert PackedDoubleword Integers toPacked Single-PrecisionFloating-Point3SSE2CVTPD2DQConvert Packed Double-Precision Floating-Pointto Packed DoublewordIntegers3SSE2CVTPD2PIConvert Packed Double-Precision Floating-Pointto Packed DoublewordIntegers3SSE2SSE2CVTPD2PSConvert Packed Double-Precision Floating-Pointto Packed Single-Precision Floating-Point3SSE2CVTPI2PDConvert PackedDoubleword Integers toPacked Double-PrecisionFloating-Point3SSE2SSE2CVTPI2PSConvert PackedDoubleword Integers toPacked Single-PrecisionFloating-Point3SSESSECVTPS2DQConvert Packed Single-Precision Floating-Pointto Packed DoublewordIntegers3SSE21. Columns indicate the instruction subsets. Entries indicate the CPUID feature set(s) to which the instruction belongs.2. Mnemonic is used for two different instructions. Assemblers can distinguish them by the number and type of operands.Appendix D: Instruction Subsets and CPUID Feature Sets 461
- Page 440 and 441: AMD64 Technology 24594 Rev. 3.10 Fe
- Page 442 and 443: AMD64 Technology 24594 Rev. 3.10 Fe
- Page 444 and 445: AMD64 Technology 24594 Rev. 3.10 Fe
- Page 446 and 447: AMD64 Technology 24594 Rev. 3.10 Fe
- Page 448 and 449: AMD64 Technology 24594 Rev. 3.10 Fe
- Page 450 and 451: AMD64 Technology 24594 Rev. 3.10 Fe
- Page 452 and 453: AMD64 Technology 24594 Rev. 3.10 Fe
- Page 454 and 455: AMD64 Technology 24594 Rev. 3.10 Fe
- Page 456 and 457: AMD64 Technology 24594 Rev. 3.10 Fe
- Page 458 and 459: AMD64 Technology 24594 Rev. 3.10 Fe
- Page 460 and 461: AMD64 Technology 24594 Rev. 3.10 Fe
- Page 462 and 463: AMD64 Technology 24594 Rev. 3.10 Fe
- Page 464 and 465: AMD64 Technology 24594 Rev. 3.10 Fe
- Page 466 and 467: AMD64 Technology 24594 Rev. 3.10 Fe
- Page 468 and 469: AMD64 Technology 24594 Rev. 3.10 Fe
- Page 470 and 471: AMD64 Technology 24594 Rev. 3.10 Fe
- Page 472 and 473: AMD64 Technology 24594 Rev. 3.10 Fe
- Page 474 and 475: AMD64 Technology 24594 Rev. 3.10 Fe
- Page 476 and 477: AMD64 Technology 24594 Rev. 3.10 Fe
- Page 478 and 479: AMD64 Technology 24594 Rev. 3.10 Fe
- Page 480 and 481: AMD64 Technology 24594 Rev. 3.10 Fe
- Page 482 and 483: AMD64 Technology 24594 Rev. 3.10 Fe
- Page 484 and 485: AMD64 Technology 24594 Rev. 3.10 Fe
- Page 486 and 487: AMD64 Technology 24594 Rev. 3.10 Fe
- Page 488 and 489: AMD64 Technology 24594 Rev. 3.10 Fe
- Page 492 and 493: AMD64 Technology 24594 Rev. 3.10 Fe
- Page 494 and 495: AMD64 Technology 24594 Rev. 3.10 Fe
- Page 496 and 497: AMD64 Technology 24594 Rev. 3.10 Fe
- Page 498 and 499: AMD64 Technology 24594 Rev. 3.10 Fe
- Page 500 and 501: AMD64 Technology 24594 Rev. 3.10 Fe
- Page 502 and 503: AMD64 Technology 24594 Rev. 3.10 Fe
- Page 504 and 505: AMD64 Technology 24594 Rev. 3.10 Fe
- Page 506 and 507: AMD64 Technology 24594 Rev. 3.10 Fe
- Page 508 and 509: AMD64 Technology 24594 Rev. 3.10 Fe
- Page 510 and 511: AMD64 Technology 24594 Rev. 3.10 Fe
- Page 512 and 513: AMD64 Technology 24594 Rev. 3.10 Fe
- Page 514 and 515: AMD64 Technology 24594 Rev. 3.10 Fe
- Page 516 and 517: AMD64 Technology 24594 Rev. 3.10 Fe
- Page 518 and 519: AMD64 Technology 24594 Rev. 3.10 Fe
- Page 520 and 521: AMD64 Technology 24594 Rev. 3.10 Fe
- Page 522 and 523: AMD64 Technology 24594 Rev. 3.10 Fe
- Page 524 and 525: AMD64 Technology 24594 Rev. 3.10 Fe
- Page 526 and 527: AMD64 Technology 24594 Rev. 3.10 Fe
- Page 528 and 529: AMD64 Technology 24594 Rev. 3.10 Fe
- Page 530 and 531: AMD64 Technology 24594 Rev. 3.10 Fe
- Page 532 and 533: AMD64 Technology 24594 Rev. 3.10 Fe
- Page 534: AMD64 Technology 24594 Rev. 3.10 Fe
AMD64 Technology 24594 Rev. 3.10 February 2005Table D-1.Instruction Subsets <strong>and</strong> CPUID Feature Sets (continued)CMPPSCompare Packed Single-Precision Floating-PointCMPS Compare Strings 3 BasicCMPSB Compare Strings by Byte 3 BasicCMPSDCMPSDCMPSQCMPSSCMPSWCompare Strings byDoublewordCompare Scalar Double-Precision Floating-PointCompare Strings byQuadwordCompare Scalar Single-Precision Floating-PointCompare Strings byWord333333Basic 2Long ModeBasicCMPXCHG Compare <strong>and</strong> Exchange 3 BasicCMPXCHG8BCMPXCHG16BCOMISDCOMISSCompare <strong>and</strong> ExchangeEight BytesCompare <strong>and</strong> ExchangeSixteen BytesCompare Ordered ScalarDouble-PrecisionFloating-PointCompare Ordered ScalarSingle-PrecisionFloating-Point333CMPXCHG8BCMPXCHG16BCPUID Processor Identification 3 BasicCQOInstructionMnemonic Description CPLConvert Quadword toDouble Quadword33<strong>General</strong>-<strong>Purpose</strong>Long ModeInstruction Subset<strong>and</strong> CPUID Feature Set(s) 1128-BitMediaSSESSE2 2SSESSE2SSE64-BitMediax87<strong>System</strong>1. Columns indicate the instruction subsets. Entries indicate the CPUID feature set(s) to which the instruction belongs.2. Mnemonic is used for two different instructions. Assemblers can distinguish them by the number <strong>and</strong> type of oper<strong>and</strong>s.460 Appendix D: Instruction Subsets <strong>and</strong> CPUID Feature Sets
Change language