Volume 3: General-Purpose and System Instructions - Stanford ...

AMD64 Technology 24594 Rev. 3.10 February 2005Table D-1.Instruction Subsets and CPUID Feature Sets (continued)ADD Signed or Unsigned Add 3 BasicADDPDADDPSADDSDADDSSADDSUBPDADDSUBPSAdd Packed Double-Precision Floating-PointAdd Packed Single-Precision Floating-PointAdd Scalar Double-Precision Floating-PointAdd Scalar Single-Precision Floating-PointAdd and SubtractDouble-PrecisionAdd and Subtract Single-PrecisionAND Logical AND 3 BasicANDNPDANDNPSANDPDANDPSARPLInstructionMnemonic Description CPLLogical Bitwise AND NOTPacked Double-PrecisionFloating-PointLogical Bitwise AND NOTPacked Single-PrecisionFloating-PointLogical Bitwise ANDPacked Double-PrecisionFloating-PointLogical Bitwise ANDPacked Single-PrecisionFloating-PointAdjust RequestorPrivilege Level33333333333General-PurposeBOUND Check Array Bounds 3 BasicInstruction Subsetand CPUID Feature Set(s) 1128-BitMediaSSE2SSESSE2SSESSE3SSE3SSE2SSESSE2SSE64-BitMediax87SystemBasic1. Columns indicate the instruction subsets. Entries indicate the CPUID feature set(s) to which the instruction belongs.2. Mnemonic is used for two different instructions. Assemblers can distinguish them by the number and type of operands.458 Appendix D: Instruction Subsets and CPUID Feature Sets