Volume 3: General-Purpose and System Instructions - Stanford ...
Volume 3: General-Purpose and System Instructions - Stanford ... Volume 3: General-Purpose and System Instructions - Stanford ...
AMD64 Technology 24594 Rev. 3.10 February 2005General-Purpose InstructionsBasicInstructionsLong-ModeInstructionsSystem Instructionsx87 Instructionsx87 InstructionsMMXInstructionsAMD Extensionsto MMXInstructionsSSEInstructionsSSE3Instructions64-Bit MediaInstructions128-Bit MediaInstructionsAMD 3DNow!InstructionsAMD Extensionto3DNow!InstructionsTime of IntroductionSSE2InstructionsDashed-line boxes show instruction subsets.Circles show major CPUID feature sets.(Minor features sets are not shown.)Figure D-1.Instruction Subsets vs. CPUID Feature Sets454 Appendix D: Instruction Subsets and CPUID Feature Sets
24594 Rev. 3.10 February 2005 AMD64 TechnologyD.2 CPUID Feature SetsThe CPUID feature sets shown in Figure D-1 and listed inTable D-1 on page 457 include:• Basic Instructions—Instructions that are supported in allhardware implementations of the AMD64 architecture,except that the following instructions are implemented onlyif their associated CPUID function bit is set:- CLFLUSH, indicated by EDX bit 19 of CPUID standardfunction 1.- CMPXCHG8B, indicated by EDX bit 8 of CPUIDstandard function 1 and extended function 8000_0001h.- CMPXCHG16B, indicated by ECX bit 13 of CPUIDstandard function 1.- CMOVcc (conditional moves), indicated by EDX bit 15 ofCPUID standard function 1 and extended function8000_0001h.- RDMSR and WRMSR, indicated by EDX bit 5 of CPUIDstandard function 1 and extended function 8000_0001h.- RDTSC, indicated by EDX bit 4 of CPUID standardfunction 1 and extended function 8000_0001h.- RDTSCP, indicated by EDX bit 27 of CPUID extendedfunction 8000_0001h.- SYSCALL and SYSRET, indicated by EDX bit 11 ofCPUID extended function 8000_0001h.- SYSENTER and SYSEXIT, indicated by EDX bit 11 ofCPUID standard function 1.• x87 Instructions—Legacy floating-point instructions that usethe ST(0)–ST(7) stack registers (FPR0–FPR7 physicalregisters) and are supported if the following bits are set:- On-chip floating-point unit, indicated by EDX bit 0 ofCPUID standard function 1 and extended function8000_0001h.- FCMOVcc (conditional moves), indicated by EDX bit 15of CPUID standard function 1 and extended function8000_0001h. This bit indicates support for x87 floatingpointconditional moves (FCMOVcc) whenever the On-Chip Floating-Point Unit bit (bit 0) is also set.• MMX Instructions—Vector integer instructions that areimplemented in the MMX instruction set, use the MMXAppendix D: Instruction Subsets and CPUID Feature Sets 455
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AMD64 Technology 24594 Rev. 3.10 February 2005<strong>General</strong>-<strong>Purpose</strong> <strong>Instructions</strong>Basic<strong>Instructions</strong>Long-Mode<strong>Instructions</strong><strong>System</strong> <strong>Instructions</strong>x87 <strong>Instructions</strong>x87 <strong>Instructions</strong>MMX<strong>Instructions</strong>AMD Extensionsto MMX<strong>Instructions</strong>SSE<strong>Instructions</strong>SSE3<strong>Instructions</strong>64-Bit Media<strong>Instructions</strong>128-Bit Media<strong>Instructions</strong>AMD 3DNow!<strong>Instructions</strong>AMD Extensionto3DNow!<strong>Instructions</strong>Time of IntroductionSSE2<strong>Instructions</strong>Dashed-line boxes show instruction subsets.Circles show major CPUID feature sets.(Minor features sets are not shown.)Figure D-1.Instruction Subsets vs. CPUID Feature Sets454 Appendix D: Instruction Subsets <strong>and</strong> CPUID Feature Sets
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