Volume 3: General-Purpose and System Instructions - Stanford ...
Volume 3: General-Purpose and System Instructions - Stanford ... Volume 3: General-Purpose and System Instructions - Stanford ...
AMD64 Technology 24594 Rev. 3.10 February 2005Table B-1.Operations and Operands in 64-Bit Mode (continued)Instruction andOpcode (hex) 1Type ofOperation 2DefaultOperandSize 3For 32-BitOperand Size 4For 64-BitOperand Size 4RDPMC—Read Performance-MonitoringCounters0F 33Same aslegacy mode.Not relevant.RDX[31:0] contains PMC[63:32],RAX[31:0] contains PMC[31:0]. Zeroextends32-bit register results to 64bits.RDTSC—Read Time-Stamp Counter0F 31Same aslegacy mode.Not relevant.RDX[31:0] contains TSC[63:32],RAX[31:0] contains TSC[31:0]. Zeroextends32-bit register results to 64bits.RDTSCP—Read Time-Stamp Counter andProcessor ID0F 01 F9Same aslegacy mode.Not relevant.RDX[31:0] contains TSC[63:32],RAX[31:0] contains TSC[31:0].RCX[31:0] contains the TSC_AUX MSRC000_0103h[31:0]. Zero-extends 32-bitregister results to 64 bits.REP INS—Repeat Input StringF3 6DSame aslegacy mode.32 bitsReads doubleword I/O port.See footnote 5REP LODS—Repeat Load StringF3 ADPromoted to64 bits.32 bitsZero-extends EAXto 64 bits.See footnote 5 See footnote 5REP MOVS—Repeat Move StringF3 A5Promoted to64 bits.32 bitsNo GPR register results.See footnote 5REP OUTS—Repeat Output String to PortF3 6FSame aslegacy mode.32 bitsWrites doubleword to I/O port.No GPR register results.See footnote 5Note:1. See “General Rules for 64-Bit Mode” on page 413, for opcodes that do not appear in this table.2. The type of operation, excluding considerations of operand size or extension of results. See “General Rules for 64-Bit Mode” onpage 413 for definitions of “Promoted to 64 bits” and related topics.3. If “Type of Operation” is 64 bits, a REX prefix is needed for 64-bit operand size, unless the instruction size defaults to 64 bits. Ifthe operand size is fixed, operand-size overrides are silently ignored.4. Special actions in 64-bit mode, in addition to legacy-mode actions. Zero or sign extensions apply only to result operands, notsource operands. Unless otherwise stated, 8-bit and 16-bit results leave the high 56 or 48 bits, respectively, of 64-bit destinationregisters unchanged. Immediates and branch displacements are sign-extended to 64 bits.5. Any pointer registers (rDI, rSI) or count registers (rCX) are address-sized and default to 64 bits. For 32-bit address size, any pointerand count registers are zero-extended to 64 bits.6. The default operand size can be overridden to 16 bits with 66h prefix, but there is no 32-bit operand-size override in 64-bit mode.436 Appendix B: General-Purpose Instructions in 64-Bit Mode
24594 Rev. 3.10 February 2005 AMD64 TechnologyTable B-1.Operations and Operands in 64-Bit Mode (continued)Instruction andOpcode (hex) 1Type ofOperation 2DefaultOperandSize 3For 32-BitOperand Size 4For 64-BitOperand Size 4REP STOS—Repeat Store StringF3 ABPromoted to64 bits.32 bitsNo GPR register results.See footnote 5REPx CMPS —Repeat Compare StringF3 A7Promoted to64 bits.32 bitsNo GPR register results.See footnote 5REPx SCAS —Repeat Scan StringF3 AFPromoted to64 bits.32 bitsNo GPR register results.See footnote 5RET—Return from Call Near See “Near Branches in 64-Bit Mode” in Volume 1.C2C3Promoted to64 bits.64 bits Cannot encode. 6 No GPR registerresults.RET—Return from Call FarCBCAPromoted to64 bits.32 bitsSee “Control Transfers” in Volume 1and “Control-Transfer PrivilegeChecks” in Volume 2.ROL—Rotate LeftD1 /0D3 /0Promoted to64 bits.32 bitsZero-extends 32-bit register resultsto 64 bits.Uses 6-bit count.C1 /0Note:1. See “General Rules for 64-Bit Mode” on page 413, for opcodes that do not appear in this table.2. The type of operation, excluding considerations of operand size or extension of results. See “General Rules for 64-Bit Mode” onpage 413 for definitions of “Promoted to 64 bits” and related topics.3. If “Type of Operation” is 64 bits, a REX prefix is needed for 64-bit operand size, unless the instruction size defaults to 64 bits. Ifthe operand size is fixed, operand-size overrides are silently ignored.4. Special actions in 64-bit mode, in addition to legacy-mode actions. Zero or sign extensions apply only to result operands, notsource operands. Unless otherwise stated, 8-bit and 16-bit results leave the high 56 or 48 bits, respectively, of 64-bit destinationregisters unchanged. Immediates and branch displacements are sign-extended to 64 bits.5. Any pointer registers (rDI, rSI) or count registers (rCX) are address-sized and default to 64 bits. For 32-bit address size, any pointerand count registers are zero-extended to 64 bits.6. The default operand size can be overridden to 16 bits with 66h prefix, but there is no 32-bit operand-size override in 64-bit mode.Appendix B: General-Purpose Instructions in 64-Bit Mode 437
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24594 Rev. 3.10 February 2005 AMD64 TechnologyTable B-1.Operations <strong>and</strong> Oper<strong>and</strong>s in 64-Bit Mode (continued)Instruction <strong>and</strong>Opcode (hex) 1Type ofOperation 2DefaultOper<strong>and</strong>Size 3For 32-BitOper<strong>and</strong> Size 4For 64-BitOper<strong>and</strong> Size 4REP STOS—Repeat Store StringF3 ABPromoted to64 bits.32 bitsNo GPR register results.See footnote 5REPx CMPS —Repeat Compare StringF3 A7Promoted to64 bits.32 bitsNo GPR register results.See footnote 5REPx SCAS —Repeat Scan StringF3 AFPromoted to64 bits.32 bitsNo GPR register results.See footnote 5RET—Return from Call Near See “Near Branches in 64-Bit Mode” in <strong>Volume</strong> 1.C2C3Promoted to64 bits.64 bits Cannot encode. 6 No GPR registerresults.RET—Return from Call FarCBCAPromoted to64 bits.32 bitsSee “Control Transfers” in <strong>Volume</strong> 1<strong>and</strong> “Control-Transfer PrivilegeChecks” in <strong>Volume</strong> 2.ROL—Rotate LeftD1 /0D3 /0Promoted to64 bits.32 bitsZero-extends 32-bit register resultsto 64 bits.Uses 6-bit count.C1 /0Note:1. See “<strong>General</strong> Rules for 64-Bit Mode” on page 413, for opcodes that do not appear in this table.2. The type of operation, excluding considerations of oper<strong>and</strong> size or extension of results. See “<strong>General</strong> Rules for 64-Bit Mode” onpage 413 for definitions of “Promoted to 64 bits” <strong>and</strong> related topics.3. If “Type of Operation” is 64 bits, a REX prefix is needed for 64-bit oper<strong>and</strong> size, unless the instruction size defaults to 64 bits. Ifthe oper<strong>and</strong> size is fixed, oper<strong>and</strong>-size overrides are silently ignored.4. Special actions in 64-bit mode, in addition to legacy-mode actions. Zero or sign extensions apply only to result oper<strong>and</strong>s, notsource oper<strong>and</strong>s. Unless otherwise stated, 8-bit <strong>and</strong> 16-bit results leave the high 56 or 48 bits, respectively, of 64-bit destinationregisters unchanged. Immediates <strong>and</strong> branch displacements are sign-extended to 64 bits.5. Any pointer registers (rDI, rSI) or count registers (rCX) are address-sized <strong>and</strong> default to 64 bits. For 32-bit address size, any pointer<strong>and</strong> count registers are zero-extended to 64 bits.6. The default oper<strong>and</strong> size can be overridden to 16 bits with 66h prefix, but there is no 32-bit oper<strong>and</strong>-size override in 64-bit mode.Appendix B: <strong>General</strong>-<strong>Purpose</strong> <strong>Instructions</strong> in 64-Bit Mode 437
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