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Volume 3: General-Purpose and System Instructions - Stanford ...

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24594 Rev. 3.10 February 2005 AMD64 TechnologyTable B-1.Operations <strong>and</strong> Oper<strong>and</strong>s in 64-Bit Mode (continued)PUSHA, PUSHAD - Push All to GPR Wordsor Doublewords60PUSHF, PUSHFD, PUSHFQ—Push rFLAGSWord, Doubleword, or Quadword ontoStack9CRCL—Rotate Through Carry LeftD1 /2D3 /2C1 /2RCR—Rotate Through Carry RightD1 /3D3 /3C1 /3RDMSR—Read Model-Specific Register0F 32Instruction <strong>and</strong>Opcode (hex) 1Type ofOperation 2Promoted to64 bits.Promoted to64 bits.Promoted to64 bits.Same aslegacy mode.DefaultOper<strong>and</strong>Size 3INVALID IN 64-BIT MODE (invalid-opcode exception)64 bits Cannot encode 6 mnemonic):Pushes the 64-bitPUSHFQ (newRFLAGS register.32 bits32 bitsNot relevant.For 32-BitOper<strong>and</strong> Size 4Zero-extends 32-bit register resultsto 64 bits.Zero-extends 32-bit register resultsto 64 bits.For 64-BitOper<strong>and</strong> Size 4Uses 6-bit count.Uses 6-bit count.RDX[31:0] contains MSR[63:32],RAX[31:0] contains MSR[31:0]. Zeroextends32-bit register results to 64bits.Note:1. See “<strong>General</strong> Rules for 64-Bit Mode” on page 413, for opcodes that do not appear in this table.2. The type of operation, excluding considerations of oper<strong>and</strong> size or extension of results. See “<strong>General</strong> Rules for 64-Bit Mode” onpage 413 for definitions of “Promoted to 64 bits” <strong>and</strong> related topics.3. If “Type of Operation” is 64 bits, a REX prefix is needed for 64-bit oper<strong>and</strong> size, unless the instruction size defaults to 64 bits. Ifthe oper<strong>and</strong> size is fixed, oper<strong>and</strong>-size overrides are silently ignored.4. Special actions in 64-bit mode, in addition to legacy-mode actions. Zero or sign extensions apply only to result oper<strong>and</strong>s, notsource oper<strong>and</strong>s. Unless otherwise stated, 8-bit <strong>and</strong> 16-bit results leave the high 56 or 48 bits, respectively, of 64-bit destinationregisters unchanged. Immediates <strong>and</strong> branch displacements are sign-extended to 64 bits.5. Any pointer registers (rDI, rSI) or count registers (rCX) are address-sized <strong>and</strong> default to 64 bits. For 32-bit address size, any pointer<strong>and</strong> count registers are zero-extended to 64 bits.6. The default oper<strong>and</strong> size can be overridden to 16 bits with 66h prefix, but there is no 32-bit oper<strong>and</strong>-size override in 64-bit mode.Appendix B: <strong>General</strong>-<strong>Purpose</strong> <strong>Instructions</strong> in 64-Bit Mode 435

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