Volume 3: General-Purpose and System Instructions - Stanford ...
Volume 3: General-Purpose and System Instructions - Stanford ... Volume 3: General-Purpose and System Instructions - Stanford ...
AMD64 Technology 24594 Rev. 3.10 February 2005Table B-1.Operations and Operands in 64-Bit Mode (continued)IRET, IRETD, IRETQ—Interrupt ReturnCFPromoted to64 bits.32 bitsIRETD: InterruptReturnDoubleword.See “Long-ModeInterrupt ControlTransfers” inVolume 2.Jcc—Jump Conditional See “Near Branches in 64-Bit Mode” in Volume 1.70 through 7F0F 80 through 0F 8FJCXZ, JECXZ, JRCXZ—Jump on CX/ECX/RCXZeroE3Instruction andOpcode (hex) 1Type ofOperation 2Promoted to64 bits.Promoted to64 bits.DefaultOperandSize 3For 32-BitOperand Size 4For 64-BitOperand Size 4IRETQ (newmnemonic):Interrupt ReturnQuadword.See “Long-ModeInterrupt ControlTransfers” inVolume 2.64 bits 6 RIP = RIP + 8-bitdisplacementsign-extended to64 bits.RIP = RIP + 32-bitdisplacementsign-extended to64 bits.64 bits Can’t encode. 6 RIP = RIP + 8-bitdisplacementsign-extended to64 bits.See footnote 5Note:1. See “General Rules for 64-Bit Mode” on page 413, for opcodes that do not appear in this table.2. The type of operation, excluding considerations of operand size or extension of results. See “General Rules for 64-Bit Mode” onpage 413 for definitions of “Promoted to 64 bits” and related topics.3. If “Type of Operation” is 64 bits, a REX prefix is needed for 64-bit operand size, unless the instruction size defaults to 64 bits. Ifthe operand size is fixed, operand-size overrides are silently ignored.4. Special actions in 64-bit mode, in addition to legacy-mode actions. Zero or sign extensions apply only to result operands, notsource operands. Unless otherwise stated, 8-bit and 16-bit results leave the high 56 or 48 bits, respectively, of 64-bit destinationregisters unchanged. Immediates and branch displacements are sign-extended to 64 bits.5. Any pointer registers (rDI, rSI) or count registers (rCX) are address-sized and default to 64 bits. For 32-bit address size, any pointerand count registers are zero-extended to 64 bits.6. The default operand size can be overridden to 16 bits with 66h prefix, but there is no 32-bit operand-size override in 64-bit mode.424 Appendix B: General-Purpose Instructions in 64-Bit Mode
24594 Rev. 3.10 February 2005 AMD64 TechnologyTable B-1.Operations and Operands in 64-Bit Mode (continued)JMP—Jump Near See “Near Branches in 64-Bit Mode” in Volume 1.EBE9FF /4Promoted to64 bits.JMP—Jump Far See “Branches to 64-Bit Offsets” in Volume 1.EAFF /5LAHF - Load Status Flags into AH Register9FLAR—Load Access Rights Byte0F 02Instruction andOpcode (hex) 1Type ofOperation 2Promoted to64 bits.Same as legacymode.Same aslegacy mode.DefaultOperandSize 364 bits Can’t encode. 6 RIP = RIP + 8-bitdisplacementsign-extended to64 bits.RIP = RIP + 32-bitdisplacementsign-extended to64 bits.INVALID IN 64-BIT MODE (invalid-opcode exception)32 bitsNot relevant.32 bitsFor 32-BitOperand Size 4RIP = 64-bit offsetfrom register ormemory.If selector points to a gate, thenRIP = 64-bit offset from gate, elseRIP = zero-extended 32-bit offset fromfar pointer referenced in instruction.Zero-extends 32-bit register resultsto 64 bits.For 64-BitOperand Size 4Note:1. See “General Rules for 64-Bit Mode” on page 413, for opcodes that do not appear in this table.2. The type of operation, excluding considerations of operand size or extension of results. See “General Rules for 64-Bit Mode” onpage 413 for definitions of “Promoted to 64 bits” and related topics.3. If “Type of Operation” is 64 bits, a REX prefix is needed for 64-bit operand size, unless the instruction size defaults to 64 bits. Ifthe operand size is fixed, operand-size overrides are silently ignored.4. Special actions in 64-bit mode, in addition to legacy-mode actions. Zero or sign extensions apply only to result operands, notsource operands. Unless otherwise stated, 8-bit and 16-bit results leave the high 56 or 48 bits, respectively, of 64-bit destinationregisters unchanged. Immediates and branch displacements are sign-extended to 64 bits.5. Any pointer registers (rDI, rSI) or count registers (rCX) are address-sized and default to 64 bits. For 32-bit address size, any pointerand count registers are zero-extended to 64 bits.6. The default operand size can be overridden to 16 bits with 66h prefix, but there is no 32-bit operand-size override in 64-bit mode.Appendix B: General-Purpose Instructions in 64-Bit Mode 425
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24594 Rev. 3.10 February 2005 AMD64 TechnologyTable B-1.Operations <strong>and</strong> Oper<strong>and</strong>s in 64-Bit Mode (continued)JMP—Jump Near See “Near Branches in 64-Bit Mode” in <strong>Volume</strong> 1.EBE9FF /4Promoted to64 bits.JMP—Jump Far See “Branches to 64-Bit Offsets” in <strong>Volume</strong> 1.EAFF /5LAHF - Load Status Flags into AH Register9FLAR—Load Access Rights Byte0F 02Instruction <strong>and</strong>Opcode (hex) 1Type ofOperation 2Promoted to64 bits.Same as legacymode.Same aslegacy mode.DefaultOper<strong>and</strong>Size 364 bits Can’t encode. 6 RIP = RIP + 8-bitdisplacementsign-extended to64 bits.RIP = RIP + 32-bitdisplacementsign-extended to64 bits.INVALID IN 64-BIT MODE (invalid-opcode exception)32 bitsNot relevant.32 bitsFor 32-BitOper<strong>and</strong> Size 4RIP = 64-bit offsetfrom register ormemory.If selector points to a gate, thenRIP = 64-bit offset from gate, elseRIP = zero-extended 32-bit offset fromfar pointer referenced in instruction.Zero-extends 32-bit register resultsto 64 bits.For 64-BitOper<strong>and</strong> Size 4Note:1. See “<strong>General</strong> Rules for 64-Bit Mode” on page 413, for opcodes that do not appear in this table.2. The type of operation, excluding considerations of oper<strong>and</strong> size or extension of results. See “<strong>General</strong> Rules for 64-Bit Mode” onpage 413 for definitions of “Promoted to 64 bits” <strong>and</strong> related topics.3. If “Type of Operation” is 64 bits, a REX prefix is needed for 64-bit oper<strong>and</strong> size, unless the instruction size defaults to 64 bits. Ifthe oper<strong>and</strong> size is fixed, oper<strong>and</strong>-size overrides are silently ignored.4. Special actions in 64-bit mode, in addition to legacy-mode actions. Zero or sign extensions apply only to result oper<strong>and</strong>s, notsource oper<strong>and</strong>s. Unless otherwise stated, 8-bit <strong>and</strong> 16-bit results leave the high 56 or 48 bits, respectively, of 64-bit destinationregisters unchanged. Immediates <strong>and</strong> branch displacements are sign-extended to 64 bits.5. Any pointer registers (rDI, rSI) or count registers (rCX) are address-sized <strong>and</strong> default to 64 bits. For 32-bit address size, any pointer<strong>and</strong> count registers are zero-extended to 64 bits.6. The default oper<strong>and</strong> size can be overridden to 16 bits with 66h prefix, but there is no 32-bit oper<strong>and</strong>-size override in 64-bit mode.Appendix B: <strong>General</strong>-<strong>Purpose</strong> <strong>Instructions</strong> in 64-Bit Mode 425
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