Volume 3: General-Purpose and System Instructions - Stanford ...
Volume 3: General-Purpose and System Instructions - Stanford ... Volume 3: General-Purpose and System Instructions - Stanford ...
AMD64 Technology 24594 Rev. 3.10 February 2005Table B-1.Operations and Operands in 64-Bit Mode (continued)Instruction andOpcode (hex) 1Type ofOperation 2DefaultOperandSize 3For 32-BitOperand Size 4For 64-BitOperand Size 4CMP—Compare393B3DPromoted to64 bits.32 bitsZero-extends 32-bit register resultsto 64 bits.81 /783 /7CMPS, CMPSW, CMPSD, CMPSQ—Compare StringsA7Promoted to64 bits.32 bitsCMPSD:Compare StringDoublewords.See footnote 5CMPSQ (newmnemonic):Compare StringQuadwordsSee footnote 5CMPXCHG—Compare and Exchange0F B1Promoted to64 bits.32 bitsZero-extends 32-bit register resultsto 64 bits.CMPXCHG8B—Compare and ExchangeEight Bytes0F C7 /1Same aslegacy mode.32 bits.Zero-extends EDXand EAX to 64bits.CMPXCHG16B(new mnemonic):Compare andExchange 16Bytes.CPUID—Processor Identification0F A2Same aslegacy mode.Operand sizefixed at 32bits.Zero-extends 32-bit register results to64 bits.Note:1. See “General Rules for 64-Bit Mode” on page 413, for opcodes that do not appear in this table.2. The type of operation, excluding considerations of operand size or extension of results. See “General Rules for 64-Bit Mode” onpage 413 for definitions of “Promoted to 64 bits” and related topics.3. If “Type of Operation” is 64 bits, a REX prefix is needed for 64-bit operand size, unless the instruction size defaults to 64 bits. Ifthe operand size is fixed, operand-size overrides are silently ignored.4. Special actions in 64-bit mode, in addition to legacy-mode actions. Zero or sign extensions apply only to result operands, notsource operands. Unless otherwise stated, 8-bit and 16-bit results leave the high 56 or 48 bits, respectively, of 64-bit destinationregisters unchanged. Immediates and branch displacements are sign-extended to 64 bits.5. Any pointer registers (rDI, rSI) or count registers (rCX) are address-sized and default to 64 bits. For 32-bit address size, any pointerand count registers are zero-extended to 64 bits.6. The default operand size can be overridden to 16 bits with 66h prefix, but there is no 32-bit operand-size override in 64-bit mode.420 Appendix B: General-Purpose Instructions in 64-Bit Mode
24594 Rev. 3.10 February 2005 AMD64 TechnologyTable B-1.Operations and Operands in 64-Bit Mode (continued)Instruction andOpcode (hex) 1Type ofOperation 2DefaultOperandSize 3For 32-BitOperand Size 4For 64-BitOperand Size 4CQO (new mnemonic)see CWD, CDQ, CQOCWD, CDQ, CQO—Convert Word toDoubleword, Convert Doubleword toQuadword, Convert Quadword to DoubleQuadword99Promoted to64 bits.32 bits(size of destinationregister)CDQ: Convertsdoubleword toquadword.Sign-extends EAXto EDX. ZeroextendsEDX toRDX. RAX isunchanged.CQO (newmnemonic):Convertsquadword todoublequadword.Sign-extends RAXto RDX. RAX isunchanged.DAA - Decimal Adjust AL after Addition27DAS - Decimal Adjust AL after Subtraction2FINVALID IN 64-BIT MODE (invalid-opcode exception)INVALID IN 64-BIT MODE (invalid-opcode exception)DEC—Decrement by 1FF /1Promoted to64 bits.32 bitsZero-extends 32-bit register resultsto 64 bits.48 through 4F OPCODE USED as REX PREFIX in 64-BIT MODEDIV—Unsigned DivideF7 /6Promoted to64 bits.32 bitsZero-extends 32-bit register resultsto 64 bits.RDX:RAX containa 64-bit quotient(RAX) and 64-bitremainder (RDX).ENTER—Create Procedure Stack FrameC8Promoted to64 bits.64 bits Can’t encode 6Note:1. See “General Rules for 64-Bit Mode” on page 413, for opcodes that do not appear in this table.2. The type of operation, excluding considerations of operand size or extension of results. See “General Rules for 64-Bit Mode” onpage 413 for definitions of “Promoted to 64 bits” and related topics.3. If “Type of Operation” is 64 bits, a REX prefix is needed for 64-bit operand size, unless the instruction size defaults to 64 bits. Ifthe operand size is fixed, operand-size overrides are silently ignored.4. Special actions in 64-bit mode, in addition to legacy-mode actions. Zero or sign extensions apply only to result operands, notsource operands. Unless otherwise stated, 8-bit and 16-bit results leave the high 56 or 48 bits, respectively, of 64-bit destinationregisters unchanged. Immediates and branch displacements are sign-extended to 64 bits.5. Any pointer registers (rDI, rSI) or count registers (rCX) are address-sized and default to 64 bits. For 32-bit address size, any pointerand count registers are zero-extended to 64 bits.6. The default operand size can be overridden to 16 bits with 66h prefix, but there is no 32-bit operand-size override in 64-bit mode.Appendix B: General-Purpose Instructions in 64-Bit Mode 421
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24594 Rev. 3.10 February 2005 AMD64 TechnologyTable B-1.Operations <strong>and</strong> Oper<strong>and</strong>s in 64-Bit Mode (continued)Instruction <strong>and</strong>Opcode (hex) 1Type ofOperation 2DefaultOper<strong>and</strong>Size 3For 32-BitOper<strong>and</strong> Size 4For 64-BitOper<strong>and</strong> Size 4CQO (new mnemonic)see CWD, CDQ, CQOCWD, CDQ, CQO—Convert Word toDoubleword, Convert Doubleword toQuadword, Convert Quadword to DoubleQuadword99Promoted to64 bits.32 bits(size of destinationregister)CDQ: Convertsdoubleword toquadword.Sign-extends EAXto EDX. ZeroextendsEDX toRDX. RAX isunchanged.CQO (newmnemonic):Convertsquadword todoublequadword.Sign-extends RAXto RDX. RAX isunchanged.DAA - Decimal Adjust AL after Addition27DAS - Decimal Adjust AL after Subtraction2FINVALID IN 64-BIT MODE (invalid-opcode exception)INVALID IN 64-BIT MODE (invalid-opcode exception)DEC—Decrement by 1FF /1Promoted to64 bits.32 bitsZero-extends 32-bit register resultsto 64 bits.48 through 4F OPCODE USED as REX PREFIX in 64-BIT MODEDIV—Unsigned DivideF7 /6Promoted to64 bits.32 bitsZero-extends 32-bit register resultsto 64 bits.RDX:RAX containa 64-bit quotient(RAX) <strong>and</strong> 64-bitremainder (RDX).ENTER—Create Procedure Stack FrameC8Promoted to64 bits.64 bits Can’t encode 6Note:1. See “<strong>General</strong> Rules for 64-Bit Mode” on page 413, for opcodes that do not appear in this table.2. The type of operation, excluding considerations of oper<strong>and</strong> size or extension of results. See “<strong>General</strong> Rules for 64-Bit Mode” onpage 413 for definitions of “Promoted to 64 bits” <strong>and</strong> related topics.3. If “Type of Operation” is 64 bits, a REX prefix is needed for 64-bit oper<strong>and</strong> size, unless the instruction size defaults to 64 bits. Ifthe oper<strong>and</strong> size is fixed, oper<strong>and</strong>-size overrides are silently ignored.4. Special actions in 64-bit mode, in addition to legacy-mode actions. Zero or sign extensions apply only to result oper<strong>and</strong>s, notsource oper<strong>and</strong>s. Unless otherwise stated, 8-bit <strong>and</strong> 16-bit results leave the high 56 or 48 bits, respectively, of 64-bit destinationregisters unchanged. Immediates <strong>and</strong> branch displacements are sign-extended to 64 bits.5. Any pointer registers (rDI, rSI) or count registers (rCX) are address-sized <strong>and</strong> default to 64 bits. For 32-bit address size, any pointer<strong>and</strong> count registers are zero-extended to 64 bits.6. The default oper<strong>and</strong> size can be overridden to 16 bits with 66h prefix, but there is no 32-bit oper<strong>and</strong>-size override in 64-bit mode.Appendix B: <strong>General</strong>-<strong>Purpose</strong> <strong>Instructions</strong> in 64-Bit Mode 421
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