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AMD64 Technology 24594 Rev. 3.10 February 2005Table B-1.Operations and Operands in 64-Bit Mode (continued)Instruction andOpcode (hex) 1Type ofOperation 2DefaultOperandSize 3For 32-BitOperand Size 4For 64-BitOperand Size 4CALL—Procedure Call Near See “Near Branches in 64-Bit Mode” in Volume 1.E8FF /2Promoted to64 bits.Promoted to64 bits.64 bits Can’t encode. 6 displacementsign-extended toRIP = RIP + 32-bit64 bits.64 bits Can’t encode. 6 from register ormemory.RIP = 64-bit offsetCALL—Procedure Call Far See “Branches to 64-Bit Offsets” in Volume 1.9AINVALID IN 64-BIT MODE (invalid-opcode exception)FF /3Promoted to64 bits.32 bitsIf selector points to a gate, thenRIP = 64-bit offset from gate, elseRIP = zero-extended 32-bit offset fromfar pointer referenced in instruction.CBW, CWDE, CDQE—Convert Byte toWord, Convert Word to Doubleword,Convert Doubleword to Quadword98Promoted to64 bits.32 bits(size of destinationregister)CWDE: Convertsword todoubleword.Zero-extends EAXto RAX.CDQE (newmnemonic):Convertsdoubleword toquadword.RAX = signextendedEAX.CDQCDQE (new mnemonic)see CWD, CDQ, CQOsee CBW, CWDE, CDQENote:1. See “General Rules for 64-Bit Mode” on page 413, for opcodes that do not appear in this table.2. The type of operation, excluding considerations of operand size or extension of results. See “General Rules for 64-Bit Mode” onpage 413 for definitions of “Promoted to 64 bits” and related topics.3. If “Type of Operation” is 64 bits, a REX prefix is needed for 64-bit operand size, unless the instruction size defaults to 64 bits. Ifthe operand size is fixed, operand-size overrides are silently ignored.4. Special actions in 64-bit mode, in addition to legacy-mode actions. Zero or sign extensions apply only to result operands, notsource operands. Unless otherwise stated, 8-bit and 16-bit results leave the high 56 or 48 bits, respectively, of 64-bit destinationregisters unchanged. Immediates and branch displacements are sign-extended to 64 bits.5. Any pointer registers (rDI, rSI) or count registers (rCX) are address-sized and default to 64 bits. For 32-bit address size, any pointerand count registers are zero-extended to 64 bits.6. The default operand size can be overridden to 16 bits with 66h prefix, but there is no 32-bit operand-size override in 64-bit mode.418 Appendix B: General-Purpose Instructions in 64-Bit Mode
24594 Rev. 3.10 February 2005 AMD64 TechnologyTable B-1.Operations and Operands in 64-Bit Mode (continued)CDWECLC—Clear Carry FlagF8CLD—Clear Direction FlagFCCLFLUSH—Cache Line Invalidate0F AE /7CLI—Clear Interrupt FlagFACLTS—Clear Task-Switched Flag in CR00F 06CMC—Complement Carry FlagF5Instruction andOpcode (hex) 1CMOVcc—Conditional Move0F 40 through 0F 4FType ofOperation 2Same aslegacy mode.Same aslegacy mode.Same aslegacy mode.Same aslegacy mode.Same aslegacy mode.Same aslegacy mode.Promoted to64 bits.DefaultOperandSize 3Not relevant.Not relevant.Not relevant.Not relevant.Not relevant.Not relevant.32 bitsFor 32-BitOperand Size 4see CBW, CWDE, CDQENo GPR register results.No GPR register results.No GPR register results.No GPR register results.No GPR register results.No GPR register results.Zero-extends 32-bit register resultsto 64 bits. Thisoccurs even if thecondition is false.For 64-BitOperand Size 4Note:1. See “General Rules for 64-Bit Mode” on page 413, for opcodes that do not appear in this table.2. The type of operation, excluding considerations of operand size or extension of results. See “General Rules for 64-Bit Mode” onpage 413 for definitions of “Promoted to 64 bits” and related topics.3. If “Type of Operation” is 64 bits, a REX prefix is needed for 64-bit operand size, unless the instruction size defaults to 64 bits. Ifthe operand size is fixed, operand-size overrides are silently ignored.4. Special actions in 64-bit mode, in addition to legacy-mode actions. Zero or sign extensions apply only to result operands, notsource operands. Unless otherwise stated, 8-bit and 16-bit results leave the high 56 or 48 bits, respectively, of 64-bit destinationregisters unchanged. Immediates and branch displacements are sign-extended to 64 bits.5. Any pointer registers (rDI, rSI) or count registers (rCX) are address-sized and default to 64 bits. For 32-bit address size, any pointerand count registers are zero-extended to 64 bits.6. The default operand size can be overridden to 16 bits with 66h prefix, but there is no 32-bit operand-size override in 64-bit mode.Appendix B: General-Purpose Instructions in 64-Bit Mode 419
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