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AMD64 Technology 24594 Rev. 3.10 February 2005Table B-1.Operations and Operands in 64-Bit Mode (continued)ADD—Signed or Unsigned Add01030581 /083 /0AND—Logical AND21232581 /483 /4ARPL - Adjust Requestor Privilege Level63BOUND - Check Array Against Bounds62Instruction andOpcode (hex) 1Type ofOperation 2Promoted to64 bits.Promoted to64 bits.DefaultOperandSize 332 bits32 bitsFor 32-BitOperand Size 4Zero-extends 32-bit register resultsto 64 bits.Zero-extends 32-bit register resultsto 64 bits.OPCODE USED as MOVSXD in 64-BIT MODEINVALID IN 64-BIT MODE (invalid-opcode exception)For 64-BitOperand Size 4BSF—Bit Scan Forward0F BCPromoted to64 bits.32 bitsZero-extends 32-bit register resultsto 64 bits.Note:1. See “General Rules for 64-Bit Mode” on page 413, for opcodes that do not appear in this table.2. The type of operation, excluding considerations of operand size or extension of results. See “General Rules for 64-Bit Mode” onpage 413 for definitions of “Promoted to 64 bits” and related topics.3. If “Type of Operation” is 64 bits, a REX prefix is needed for 64-bit operand size, unless the instruction size defaults to 64 bits. Ifthe operand size is fixed, operand-size overrides are silently ignored.4. Special actions in 64-bit mode, in addition to legacy-mode actions. Zero or sign extensions apply only to result operands, notsource operands. Unless otherwise stated, 8-bit and 16-bit results leave the high 56 or 48 bits, respectively, of 64-bit destinationregisters unchanged. Immediates and branch displacements are sign-extended to 64 bits.5. Any pointer registers (rDI, rSI) or count registers (rCX) are address-sized and default to 64 bits. For 32-bit address size, any pointerand count registers are zero-extended to 64 bits.6. The default operand size can be overridden to 16 bits with 66h prefix, but there is no 32-bit operand-size override in 64-bit mode.416 Appendix B: General-Purpose Instructions in 64-Bit Mode
24594 Rev. 3.10 February 2005 AMD64 TechnologyTable B-1.Operations and Operands in 64-Bit Mode (continued)BSR—Bit Scan Reverse0F BDBSWAP—Byte SwapBT—Bit Test0F C8 through 0F CF0F A30F BA /4BTC—Bit Test and Complement0F BB0F BA /7BTR—Bit Test and Reset0F B30F BA /6BTS—Bit Test and Set0F AB0F BA /5Instruction andOpcode (hex) 1Type ofOperation 2Promoted to64 bits.Promoted to64 bits.Promoted to64 bits.Promoted to64 bits.Promoted to64 bits.Promoted to64 bits.DefaultOperandSize 332 bits32 bitsZero-extends 32-bit register resultsto 64 bits.Zero-extends 32-bit register resultsto 64 bits.32 bits No GPR register results.32 bits32 bits32 bitsFor 32-BitOperand Size 4Zero-extends 32-bit register resultsto 64 bits.Zero-extends 32-bit register resultsto 64 bits.Zero-extends 32-bit register resultsto 64 bits.For 64-BitOperand Size 4Swap all 8 bytesof a 64-bit GPR.Note:1. See “General Rules for 64-Bit Mode” on page 413, for opcodes that do not appear in this table.2. The type of operation, excluding considerations of operand size or extension of results. See “General Rules for 64-Bit Mode” onpage 413 for definitions of “Promoted to 64 bits” and related topics.3. If “Type of Operation” is 64 bits, a REX prefix is needed for 64-bit operand size, unless the instruction size defaults to 64 bits. Ifthe operand size is fixed, operand-size overrides are silently ignored.4. Special actions in 64-bit mode, in addition to legacy-mode actions. Zero or sign extensions apply only to result operands, notsource operands. Unless otherwise stated, 8-bit and 16-bit results leave the high 56 or 48 bits, respectively, of 64-bit destinationregisters unchanged. Immediates and branch displacements are sign-extended to 64 bits.5. Any pointer registers (rDI, rSI) or count registers (rCX) are address-sized and default to 64 bits. For 32-bit address size, any pointerand count registers are zero-extended to 64 bits.6. The default operand size can be overridden to 16 bits with 66h prefix, but there is no 32-bit operand-size override in 64-bit mode.Appendix B: General-Purpose Instructions in 64-Bit Mode 417
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