Volume 3: General-Purpose and System Instructions - Stanford ...
Volume 3: General-Purpose and System Instructions - Stanford ... Volume 3: General-Purpose and System Instructions - Stanford ...
AMD64 Technology 24594 Rev. 3.10 February 2005except far branches, that implicitly reference the RSP. SeeTable B-5 on page 447 for a list of all instructions thatdefault to 64-bit operand size.• Zero-Extension of 32-Bit Results: Operations on 32-bitoperands in 64-bit mode zero-extend the high 32 bits of 64-bit GPR destination registers.• No Extension of 8-Bit and 16-Bit Results: Operations on 8-bitand 16-bit operands in 64-bit mode leave the high 56 or 48bits, respectively, of 64-bit GPR destination registersunchanged.• Shift and Rotate Counts: When the operand size is 64 bits,shifts and rotates use one additional bit (6 bits total) tospecify shift-count or rotate-count, allowing 64-bit shifts androtates.• Immediates: The maximum size of immediate operands is 32bits, except that 64-bit immediates can be MOVed into 64-bitGPRs. In 64-bit mode, when the operand size is 64 bits,immediates are sign-extended to 64 bits during use, buttheir actual size (for value representation) remains amaximum of 32 bits.• Displacements: The maximum size of an addressdisplacement is 32 bits. In 64-bit mode, displacements aresign-extended to 64 bits during use, but their actual size (forvalue representation) remains a maximum of 32 bits.• Undefined High 32 Bits After Mode Change: The processordoes not preserve the upper 32 bits of the 64-bit GPRs acrossswitches from 64-bit mode to compatibility or legacy modes.In compatibility or legacy mode, the upper 32 bits of theGPRs are undefined and not accessible to software.B.2 Operation and Operand Size in 64-Bit ModeTable B-1 on page 415 lists the integer instructions, showingoperand size in 64-bit mode and the state of the high 32 bits ofdestination registers when 32-bit operands are used. Opcodes,such as byte-operand versions of several instructions, that donot appear in Table B-1 are covered by the general rulesdescribed in “General Rules for 64-Bit Mode” on page 413.414 Appendix B: General-Purpose Instructions in 64-Bit Mode
24594 Rev. 3.10 February 2005 AMD64 TechnologyTable B-1.Operations and Operands in 64-Bit ModeInstruction andOpcode (hex) 1AAA - ASCII Adjust after Addition37AAD - ASCII Adjust AX before DivisionD5AAM - ASCII Adjust AX after MultiplyD4AAS - ASCII Adjust AL after Subtraction3FADC—Add with Carry11131581 /283 /2Type ofOperation 2Promoted to64 bits.DefaultOperandSize 3For 32-BitOperand Size 4INVALID IN 64-BIT MODE (invalid-opcode exception)INVALID IN 64-BIT MODE (invalid-opcode exception)INVALID IN 64-BIT MODE (invalid-opcode exception)INVALID IN 64-BIT MODE (invalid-opcode exception)32 bitsZero-extends 32-bit register resultsto 64 bits.For 64-BitOperand Size 4Note:1. See “General Rules for 64-Bit Mode” on page 413, for opcodes that do not appear in this table.2. The type of operation, excluding considerations of operand size or extension of results. See “General Rules for 64-Bit Mode” onpage 413 for definitions of “Promoted to 64 bits” and related topics.3. If “Type of Operation” is 64 bits, a REX prefix is needed for 64-bit operand size, unless the instruction size defaults to 64 bits. Ifthe operand size is fixed, operand-size overrides are silently ignored.4. Special actions in 64-bit mode, in addition to legacy-mode actions. Zero or sign extensions apply only to result operands, notsource operands. Unless otherwise stated, 8-bit and 16-bit results leave the high 56 or 48 bits, respectively, of 64-bit destinationregisters unchanged. Immediates and branch displacements are sign-extended to 64 bits.5. Any pointer registers (rDI, rSI) or count registers (rCX) are address-sized and default to 64 bits. For 32-bit address size, any pointerand count registers are zero-extended to 64 bits.6. The default operand size can be overridden to 16 bits with 66h prefix, but there is no 32-bit operand-size override in 64-bit mode.Appendix B: General-Purpose Instructions in 64-Bit Mode 415
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24594 Rev. 3.10 February 2005 AMD64 TechnologyTable B-1.Operations <strong>and</strong> Oper<strong>and</strong>s in 64-Bit ModeInstruction <strong>and</strong>Opcode (hex) 1AAA - ASCII Adjust after Addition37AAD - ASCII Adjust AX before DivisionD5AAM - ASCII Adjust AX after MultiplyD4AAS - ASCII Adjust AL after Subtraction3FADC—Add with Carry11131581 /283 /2Type ofOperation 2Promoted to64 bits.DefaultOper<strong>and</strong>Size 3For 32-BitOper<strong>and</strong> Size 4INVALID IN 64-BIT MODE (invalid-opcode exception)INVALID IN 64-BIT MODE (invalid-opcode exception)INVALID IN 64-BIT MODE (invalid-opcode exception)INVALID IN 64-BIT MODE (invalid-opcode exception)32 bitsZero-extends 32-bit register resultsto 64 bits.For 64-BitOper<strong>and</strong> Size 4Note:1. See “<strong>General</strong> Rules for 64-Bit Mode” on page 413, for opcodes that do not appear in this table.2. The type of operation, excluding considerations of oper<strong>and</strong> size or extension of results. See “<strong>General</strong> Rules for 64-Bit Mode” onpage 413 for definitions of “Promoted to 64 bits” <strong>and</strong> related topics.3. If “Type of Operation” is 64 bits, a REX prefix is needed for 64-bit oper<strong>and</strong> size, unless the instruction size defaults to 64 bits. Ifthe oper<strong>and</strong> size is fixed, oper<strong>and</strong>-size overrides are silently ignored.4. Special actions in 64-bit mode, in addition to legacy-mode actions. Zero or sign extensions apply only to result oper<strong>and</strong>s, notsource oper<strong>and</strong>s. Unless otherwise stated, 8-bit <strong>and</strong> 16-bit results leave the high 56 or 48 bits, respectively, of 64-bit destinationregisters unchanged. Immediates <strong>and</strong> branch displacements are sign-extended to 64 bits.5. Any pointer registers (rDI, rSI) or count registers (rCX) are address-sized <strong>and</strong> default to 64 bits. For 32-bit address size, any pointer<strong>and</strong> count registers are zero-extended to 64 bits.6. The default oper<strong>and</strong> size can be overridden to 16 bits with 66h prefix, but there is no 32-bit oper<strong>and</strong>-size override in 64-bit mode.Appendix B: <strong>General</strong>-<strong>Purpose</strong> <strong>Instructions</strong> in 64-Bit Mode 415
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