Volume 3: General-Purpose and System Instructions - Stanford ...
Volume 3: General-Purpose and System Instructions - Stanford ... Volume 3: General-Purpose and System Instructions - Stanford ...
AMD64 Technology 24594 Rev. 3.10 February 2005412 Appendix A: Opcode and Operand Encodings
24594 Rev. 3.10 February 2005 AMD64 TechnologyAppendix BGeneral-Purpose Instructions in 64-BitModeThis appendix provides details of the general-purposeinstructions in 64-bit mode and its differences from legacy andcompatibility modes. The appendix covers only the generalpurposeinstructions (those described in Chapter 3, “General-Purpose Instruction Reference”). It does not cover the 128-bitmedia, 64-bit media, or x87 floating-point instructions becausethose instructions are not affected by 64-bit mode, other than inthe access by such instructions to extended GPR and XMMregisters when using a REX prefix.B.1 General Rules for 64-Bit ModeIn 64-bit mode, the following general rules apply to instructionsand their operands:• “Promoted to 64 Bit”: If an instruction’s operand size (16-bitor 32-bit) in legacy and compatibility modes depends on theCS.D bit and the operand-size override prefix, then theoperand-size choices in 64-bit mode are extended from 16-bitand 32-bit to include 64 bits (with a REX prefix), or theoperand size is fixed at 64 bits. Such instructions are said tobe “Promoted to 64 bits” in Table B-1. However, byte-operandopcodes of such instructions are not promoted.• Byte-Operand Opcodes Not Promoted: As stated above in“Promoted to 64 Bit”, byte-operand opcodes of promotedinstructions are not promoted. Those opcodes continue tooperate only on bytes.• Fixed Operand Size: If an instruction’s operand size is fixedin legacy mode (thus, independent of CS.D and prefixoverrides), that operand size is usually fixed at the same sizein 64-bit mode. For example, CPUID operates on 32-bitoperands, irrespective of attempts to override the operandsize.• Default Operand Size: The default operand size for mostinstructions is 32 bits, and a REX prefix must be used tochange the operand size to 64 bits. However, two groups ofinstructions default to 64-bit operand size and do not need aREX prefix: (1) near branches and (2) all instructions,Appendix B: General-Purpose Instructions in 64-Bit Mode 413
- Page 392 and 393: AMD64 Technology 24594 Rev. 3.10 Fe
- Page 394 and 395: AMD64 Technology 24594 Rev. 3.10 Fe
- Page 396 and 397: AMD64 Technology 24594 Rev. 3.10 Fe
- Page 398 and 399: AMD64 Technology 24594 Rev. 3.10 Fe
- Page 400 and 401: AMD64 Technology 24594 Rev. 3.10 Fe
- Page 402 and 403: AMD64 Technology 24594 Rev. 3.10 Fe
- Page 404 and 405: AMD64 Technology 24594 Rev. 3.10 Fe
- Page 406 and 407: AMD64 Technology 24594 Rev. 3.10 Fe
- Page 408 and 409: AMD64 Technology 24594 Rev. 3.10 Fe
- Page 410 and 411: AMD64 Technology 24594 Rev. 3.10 Fe
- Page 412 and 413: AMD64 Technology 24594 Rev. 3.10 Fe
- Page 414 and 415: AMD64 Technology 24594 Rev. 3.10 Fe
- Page 416 and 417: AMD64 Technology 24594 Rev. 3.10 Fe
- Page 418 and 419: AMD64 Technology 24594 Rev. 3.10 Fe
- Page 420 and 421: AMD64 Technology 24594 Rev. 3.10 Fe
- Page 422 and 423: AMD64 Technology 24594 Rev. 3.10 Fe
- Page 424 and 425: AMD64 Technology 24594 Rev. 3.10 Fe
- Page 426 and 427: AMD64 Technology 24594 Rev. 3.10 Fe
- Page 428 and 429: AMD64 Technology 24594 Rev. 3.10 Fe
- Page 430 and 431: AMD64 Technology 24594 Rev. 3.10 Fe
- Page 432 and 433: AMD64 Technology 24594 Rev. 3.10 Fe
- Page 434 and 435: AMD64 Technology 24594 Rev. 3.10 Fe
- Page 436 and 437: AMD64 Technology 24594 Rev. 3.10 Fe
- Page 438 and 439: AMD64 Technology 24594 Rev. 3.10 Fe
- Page 440 and 441: AMD64 Technology 24594 Rev. 3.10 Fe
- Page 444 and 445: AMD64 Technology 24594 Rev. 3.10 Fe
- Page 446 and 447: AMD64 Technology 24594 Rev. 3.10 Fe
- Page 448 and 449: AMD64 Technology 24594 Rev. 3.10 Fe
- Page 450 and 451: AMD64 Technology 24594 Rev. 3.10 Fe
- Page 452 and 453: AMD64 Technology 24594 Rev. 3.10 Fe
- Page 454 and 455: AMD64 Technology 24594 Rev. 3.10 Fe
- Page 456 and 457: AMD64 Technology 24594 Rev. 3.10 Fe
- Page 458 and 459: AMD64 Technology 24594 Rev. 3.10 Fe
- Page 460 and 461: AMD64 Technology 24594 Rev. 3.10 Fe
- Page 462 and 463: AMD64 Technology 24594 Rev. 3.10 Fe
- Page 464 and 465: AMD64 Technology 24594 Rev. 3.10 Fe
- Page 466 and 467: AMD64 Technology 24594 Rev. 3.10 Fe
- Page 468 and 469: AMD64 Technology 24594 Rev. 3.10 Fe
- Page 470 and 471: AMD64 Technology 24594 Rev. 3.10 Fe
- Page 472 and 473: AMD64 Technology 24594 Rev. 3.10 Fe
- Page 474 and 475: AMD64 Technology 24594 Rev. 3.10 Fe
- Page 476 and 477: AMD64 Technology 24594 Rev. 3.10 Fe
- Page 478 and 479: AMD64 Technology 24594 Rev. 3.10 Fe
- Page 480 and 481: AMD64 Technology 24594 Rev. 3.10 Fe
- Page 482 and 483: AMD64 Technology 24594 Rev. 3.10 Fe
- Page 484 and 485: AMD64 Technology 24594 Rev. 3.10 Fe
- Page 486 and 487: AMD64 Technology 24594 Rev. 3.10 Fe
- Page 488 and 489: AMD64 Technology 24594 Rev. 3.10 Fe
- Page 490 and 491: AMD64 Technology 24594 Rev. 3.10 Fe
24594 Rev. 3.10 February 2005 AMD64 TechnologyAppendix B<strong>General</strong>-<strong>Purpose</strong> <strong>Instructions</strong> in 64-BitModeThis appendix provides details of the general-purposeinstructions in 64-bit mode <strong>and</strong> its differences from legacy <strong>and</strong>compatibility modes. The appendix covers only the generalpurposeinstructions (those described in Chapter 3, “<strong>General</strong>-<strong>Purpose</strong> Instruction Reference”). It does not cover the 128-bitmedia, 64-bit media, or x87 floating-point instructions becausethose instructions are not affected by 64-bit mode, other than inthe access by such instructions to extended GPR <strong>and</strong> XMMregisters when using a REX prefix.B.1 <strong>General</strong> Rules for 64-Bit ModeIn 64-bit mode, the following general rules apply to instructions<strong>and</strong> their oper<strong>and</strong>s:• “Promoted to 64 Bit”: If an instruction’s oper<strong>and</strong> size (16-bitor 32-bit) in legacy <strong>and</strong> compatibility modes depends on theCS.D bit <strong>and</strong> the oper<strong>and</strong>-size override prefix, then theoper<strong>and</strong>-size choices in 64-bit mode are extended from 16-bit<strong>and</strong> 32-bit to include 64 bits (with a REX prefix), or theoper<strong>and</strong> size is fixed at 64 bits. Such instructions are said tobe “Promoted to 64 bits” in Table B-1. However, byte-oper<strong>and</strong>opcodes of such instructions are not promoted.• Byte-Oper<strong>and</strong> Opcodes Not Promoted: As stated above in“Promoted to 64 Bit”, byte-oper<strong>and</strong> opcodes of promotedinstructions are not promoted. Those opcodes continue tooperate only on bytes.• Fixed Oper<strong>and</strong> Size: If an instruction’s oper<strong>and</strong> size is fixedin legacy mode (thus, independent of CS.D <strong>and</strong> prefixoverrides), that oper<strong>and</strong> size is usually fixed at the same sizein 64-bit mode. For example, CPUID operates on 32-bitoper<strong>and</strong>s, irrespective of attempts to override the oper<strong>and</strong>size.• Default Oper<strong>and</strong> Size: The default oper<strong>and</strong> size for mostinstructions is 32 bits, <strong>and</strong> a REX prefix must be used tochange the oper<strong>and</strong> size to 64 bits. However, two groups ofinstructions default to 64-bit oper<strong>and</strong> size <strong>and</strong> do not need aREX prefix: (1) near branches <strong>and</strong> (2) all instructions,Appendix B: <strong>General</strong>-<strong>Purpose</strong> <strong>Instructions</strong> in 64-Bit Mode 413