Volume 3: General-Purpose and System Instructions - Stanford ...

AMD64 Technology 24594 Rev. 3.10 February 2005A.2.5 ModRMExtensions toOpcodes 0F 01 and0F AETable A-7 shows the ModRM r/m field encodings for the 0F 01and 0F AE opcodes, shown in Table A-6. The 0F 01 /7 opcode isshared by the INVLPG, SWAPGS, and RDTSCP instructionsand the 0F AE opcode is shared by the LFENCE, MFENCE, andSFENCE instructions. The opcodes are differentiated by thefact that the binary value of the ModRM mod field is always 11for SWAPGS, RDTSCP, and the xFENCE instructions, and anyvalue except 11 for INVLPG and CLFLUSH.Table A-7.Opcode0F 01 /7mod=110F 01 /3mod=110F AE /5mod=110F AE /6mod=110F AE /7mod=11Opcode 0F 01 and 0F AE ModRM ExtensionsModRM r/m Field0 1 2 3 4 5 6 7SWAPGS RDTSCP invalid invalid invalid invalid invalid invalidinvalid invalid invalid invalid invalid invalid invalid invalidLFENCEMFENCESFENCEA.2.6 3DNow!OpcodesThe 64-bit media instructions include the MMX instructionsand the AMD 3DNow! instructions. The MMX instructions areencoded using two opcode bytes, as described in “Two-ByteOpcodes” on page 380.The 3DNow! instructions are encoded using two 0Fh opcodebytes and an immediate byte that is located at the last byteposition of the instruction encoding. Thus, the format for3DNow! instructions is:0Fh 0Fh [ModRM] [SIB] [displacement] imm8_opcodeTable A-8 on page 391 and Table A-9 on page 392 show theimmediate byte following the opcode bytes for 3DNow!instructions. In these tables, rows show the high nibble of theimmediate byte, and columns show the low nibble of theimmediate byte. Table A-8 shows the immediate bytes whoselow nibble is in the range 0–7h. Table A-9 shows the same forimmediate bytes whose low nibble is in the range 8–Fh.Byte values shown as reserved in these tables haveimplementation-specific functions, which can include aninvalid-opcode exception.390 Appendix A: Opcode and Operand Encodings